Commit cd66d5c3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-designware', 'pci/host-xgene' and 'pci/host-xilinx' into next 

* pci/host-designware:
  PCI: designware: Don't complain missing *config* reg space if va_cfg0 is set

* pci/host-xgene:
  PCI: xgene: Add support for a 64-bit prefetchable memory window
  arm64: dts: Add APM X-Gene PCIe 64-bit prefetchable window
  PCI: xgene: Drop owner assignment from platform_driver

* pci/host-xilinx:
  PCI: xilinx: Check for MSI interrupt flag before handling as INTx
parents bc0195aa 0f414212 8ef54f27 e4a8f8ee

arch/arm64/boot/dts/apm/apm-storm.dtsi

+14 −9
Original line number Diff line number Diff line
@@ -490,7 +490,8 @@ 
				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */

				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */

				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */

				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -513,8 +514,9 @@ 
			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */

				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */

			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */

				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -537,8 +539,9 @@ 
			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */

				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */

			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */

				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -561,8 +564,9 @@ 
			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */

				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */

				  0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */

			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */

				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -585,8 +589,9 @@ 
			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */

				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */

			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */

				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

drivers/pci/host/pci-xgene-msi.c

+0 −1
Original line number Diff line number Diff line
@@ -582,7 +582,6 @@ error: 
static struct platform_driver xgene_msi_driver = {

	.driver = {

		.name = "xgene-msi",

		.owner = THIS_MODULE,

		.of_match_table = xgene_msi_match_table,

	},

	.probe = xgene_msi_probe,

drivers/pci/host/pci-xgene.c

+10 −2
Original line number Diff line number Diff line
@@ -321,8 +321,16 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, 
				return ret;

			break;

		case IORESOURCE_MEM:

			xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,

						res->start - window->offset);

			if (res->flags & IORESOURCE_PREFETCH)

				xgene_pcie_setup_ob_reg(port, res, OMR2BARL,

							res->start,

							res->start -

							window->offset);

			else

				xgene_pcie_setup_ob_reg(port, res, OMR1BARL,

							res->start,

							res->start -

							window->offset);

			break;

		case IORESOURCE_BUS:

			break;

drivers/pci/host/pcie-designware.c

+1 −1
Original line number Diff line number Diff line
@@ -388,7 +388,7 @@ int dw_pcie_host_init(struct pcie_port *pp) 
		addrp = of_get_address(np, index, NULL, NULL);

		pp->cfg0_mod_base = of_read_number(addrp, ns);

		pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;

	} else {

	} else if (!pp->va_cfg0_base) {

		dev_err(pp->dev, "missing *config* reg space\n");

	}

drivers/pci/host/pcie-xilinx.c

+11 −8
Original line number Diff line number Diff line
@@ -449,6 +449,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) 
			return IRQ_HANDLED;

		}



		if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {

			/* Clear interrupt FIFO register 1 */

			pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,

				   XILINX_PCIE_REG_RPIFR1);
@@ -456,7 +457,9 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) 
			/* Handle INTx Interrupt */

			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>

				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;

		generic_handle_irq(irq_find_mapping(port->irq_domain, val));

			generic_handle_irq(irq_find_mapping(port->irq_domain,

							    val));

		}

	}



	if (status & XILINX_PCIE_INTR_MSI) {

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