Commit c7e4e0d7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v4.17-samsung' of... 

Merge tag 'clk-v4.17-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung

Pull samsung clk driver updates from Sylwester Nawrocki:

This change set includes the PLL rate definition fixes and an addition
of compile time PLL rate validation macros. It adds definitions of some
missing clocks and extends the PLL rate tables required in the sound
subsystem.

In order to handle dependencies of clocks on the power domains a clock
provider sub-driver is added for Exynos5 SoCs. In newer Exynos SoCs
there is no need to do such things as the clocks/power domain relations
are more clearly defined and better documented.

* tag 'clk-v4.17-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: (21 commits)
  clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
  clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
  clk: samsung: exynos5420: Add more entries to EPLL rate table
  clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
  clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
  clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
  clk: samsung: Add Exynos5 sub-CMU clock driver
  soc: samsung: pm_domains: Add blacklisting clock handling
  clk: samsung: Add compile time PLL rate validators
  clk: samsung: s3c2410: Fix PLL rates
  clk: samsung: exynos7: Fix PLL rates
  clk: samsung: exynos5433: Fix PLL rates
  clk: samsung: exynos5260: Fix PLL rates
  clk: samsung: exynos5250: Fix PLL rates
  clk: samsung: exynos3250: Fix PLL rates
  clk: exynos5433: Extend list of available AUD_PLL output frequencies
  clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk
  clk: samsung: Add a git tree entry to MAINTAINERS
  clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe()
  clk: samsung: Remove redundant dev_err call in exynos5433_cmu_probe()
  ...
parents 7928b2cb 182c084d

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -12189,6 +12189,7 @@ M: Tomasz Figa <tomasz.figa@gmail.com> 
M:	Chanwoo Choi <cw00.choi@samsung.com>

S:	Supported

L:	linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git

F:	drivers/clk/samsung/

F:	include/dt-bindings/clock/exynos*.h

F:	Documentation/devicetree/bindings/clock/exynos*.txt

drivers/clk/samsung/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -8,9 +8,11 @@ obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o 
obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4412-isp.o

obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o

obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5-subcmu.o

obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o

obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o

obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o

obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5-subcmu.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos5433.o

obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o

obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o

drivers/clk/samsung/clk-exynos-audss.c

+1 −3
Original line number Diff line number Diff line
@@ -143,10 +143,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) 


	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	reg_base = devm_ioremap_resource(dev, res);

	if (IS_ERR(reg_base)) {

		dev_err(dev, "failed to map audss registers\n");

	if (IS_ERR(reg_base))

		return PTR_ERR(reg_base);

	}



	epll = ERR_PTR(-ENODEV);

drivers/clk/samsung/clk-exynos3250.c

+57 −57
Original line number Diff line number Diff line
@@ -670,73 +670,73 @@ static const struct samsung_gate_clock gate_clks[] __initconst = { 


/* APLL & MPLL & BPLL & UPLL */

static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {

	PLL_35XX_RATE(1200000000, 400, 4, 1),

	PLL_35XX_RATE(1100000000, 275, 3, 1),

	PLL_35XX_RATE(1066000000, 533, 6, 1),

	PLL_35XX_RATE(1000000000, 250, 3, 1),

	PLL_35XX_RATE( 960000000, 320, 4, 1),

	PLL_35XX_RATE( 900000000, 300, 4, 1),

	PLL_35XX_RATE( 850000000, 425, 6, 1),

	PLL_35XX_RATE( 800000000, 200, 3, 1),

	PLL_35XX_RATE( 700000000, 175, 3, 1),

	PLL_35XX_RATE( 667000000, 667, 12, 1),

	PLL_35XX_RATE( 600000000, 400, 4, 2),

	PLL_35XX_RATE( 533000000, 533, 6, 2),

	PLL_35XX_RATE( 520000000, 260, 3, 2),

	PLL_35XX_RATE( 500000000, 250, 3, 2),

	PLL_35XX_RATE( 400000000, 200, 3, 2),

	PLL_35XX_RATE( 200000000, 200, 3, 3),

	PLL_35XX_RATE( 100000000, 200, 3, 4),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  960000000, 320, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  900000000, 300, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  850000000, 425, 6, 1),

	PLL_35XX_RATE(24 * MHZ,  800000000, 200, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  667000000, 667, 12, 1),

	PLL_35XX_RATE(24 * MHZ,  600000000, 400, 4, 2),

	PLL_35XX_RATE(24 * MHZ,  533000000, 533, 6, 2),

	PLL_35XX_RATE(24 * MHZ,  520000000, 260, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  500000000, 250, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  400000000, 200, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  200000000, 200, 3, 3),

	PLL_35XX_RATE(24 * MHZ,  100000000, 200, 3, 4),

	{ /* sentinel */ }

};



/* EPLL */

static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {

	PLL_36XX_RATE(800000000, 200, 3, 1,     0),

	PLL_36XX_RATE(288000000,  96, 2, 2,     0),

	PLL_36XX_RATE(192000000, 128, 2, 3,     0),

	PLL_36XX_RATE(144000000,  96, 2, 3,     0),

	PLL_36XX_RATE( 96000000, 128, 2, 4,     0),

	PLL_36XX_RATE( 84000000, 112, 2, 4,     0),

	PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),

	PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),

	PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),

	PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),

	PLL_36XX_RATE( 50000000, 200, 3, 5,     0),

	PLL_36XX_RATE( 49152002, 131, 2, 5,  4719),

	PLL_36XX_RATE( 48000000, 128, 2, 5,     0),

	PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),

	PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 288000000,  96, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 144000000,  96, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ,  96000000, 128, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  84000000, 112, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  80000003, 106, 2, 4, 43691),

	PLL_36XX_RATE(24 * MHZ,  73728000,  98, 2, 4, 19923),

	PLL_36XX_RATE(24 * MHZ,  67737598, 270, 3, 5, 62285),

	PLL_36XX_RATE(24 * MHZ,  65535999, 174, 2, 5, 49982),

	PLL_36XX_RATE(24 * MHZ,  50000000, 200, 3, 5,     0),

	PLL_36XX_RATE(24 * MHZ,  49152002, 131, 2, 5,  4719),

	PLL_36XX_RATE(24 * MHZ,  48000000, 128, 2, 5,     0),

	PLL_36XX_RATE(24 * MHZ,  45158401, 180, 3, 5, 41524),

	{ /* sentinel */ }

};



/* VPLL */

static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {

	PLL_36XX_RATE(600000000, 100, 2, 1,     0),

	PLL_36XX_RATE(533000000, 266, 3, 2, 32768),

	PLL_36XX_RATE(519230987, 173, 2, 2,  5046),

	PLL_36XX_RATE(500000000, 250, 3, 2,     0),

	PLL_36XX_RATE(445500000, 148, 2, 2, 32768),

	PLL_36XX_RATE(445055007, 148, 2, 2, 23047),

	PLL_36XX_RATE(400000000, 200, 3, 2,     0),

	PLL_36XX_RATE(371250000, 123, 2, 2, 49152),

	PLL_36XX_RATE(370878997, 185, 3, 2, 28803),

	PLL_36XX_RATE(340000000, 170, 3, 2,     0),

	PLL_36XX_RATE(335000015, 111, 2, 2, 43691),

	PLL_36XX_RATE(333000000, 111, 2, 2,     0),

	PLL_36XX_RATE(330000000, 110, 2, 2,     0),

	PLL_36XX_RATE(320000015, 106, 2, 2, 43691),

	PLL_36XX_RATE(300000000, 100, 2, 2,     0),

	PLL_36XX_RATE(275000000, 275, 3, 3,     0),

	PLL_36XX_RATE(222750000, 148, 2, 3, 32768),

	PLL_36XX_RATE(222528007, 148, 2, 3, 23069),

	PLL_36XX_RATE(160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(148500000,  99, 2, 3,     0),

	PLL_36XX_RATE(148352005,  98, 2, 3, 59070),

	PLL_36XX_RATE(108000000, 144, 2, 4,     0),

	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),

	PLL_36XX_RATE( 74176002,  98, 3, 4, 59070),

	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),

	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),

	PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),

	PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2,  5046),

	PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),

	PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),

	PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),

	PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),

	PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),

	PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),

	PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),

	PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),

	PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 148500000,  99, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 148352005,  98, 2, 3, 59070),

	PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  74250000,  99, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  74176002,  98, 2, 4, 59070),

	PLL_36XX_RATE(24 * MHZ,  54054000, 216, 3, 5, 14156),

	PLL_36XX_RATE(24 * MHZ,  54000000, 144, 2, 5,     0),

	{ /* sentinel */ }

};

drivers/clk/samsung/clk-exynos4.c

+52 −51
Original line number Diff line number Diff line
@@ -1266,77 +1266,78 @@ static const struct of_device_id ext_clk_match[] __initconst = { 


/* PLLs PMS values */

static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {

	PLL_45XX_RATE(1200000000, 150,  3, 1, 28),

	PLL_45XX_RATE(1000000000, 250,  6, 1, 28),

	PLL_45XX_RATE( 800000000, 200,  6, 1, 28),

	PLL_45XX_RATE( 666857142, 389, 14, 1, 13),

	PLL_45XX_RATE( 600000000, 100,  4, 1, 13),

	PLL_45XX_RATE( 533000000, 533, 24, 1,  5),

	PLL_45XX_RATE( 500000000, 250,  6, 2, 28),

	PLL_45XX_RATE( 400000000, 200,  6, 2, 28),

	PLL_45XX_RATE( 200000000, 200,  6, 3, 28),

	PLL_4508_RATE(24 * MHZ, 1200000000, 150,  3, 1, 28),

	PLL_4508_RATE(24 * MHZ, 1000000000, 250,  6, 1, 28),

	PLL_4508_RATE(24 * MHZ,  800000000, 200,  6, 1, 28),

	PLL_4508_RATE(24 * MHZ,  666857142, 389, 14, 1, 13),

	PLL_4508_RATE(24 * MHZ,  600000000, 100,  4, 1, 13),

	PLL_4508_RATE(24 * MHZ,  533000000, 533, 24, 1,  5),

	PLL_4508_RATE(24 * MHZ,  500000000, 250,  6, 2, 28),

	PLL_4508_RATE(24 * MHZ,  400000000, 200,  6, 2, 28),

	PLL_4508_RATE(24 * MHZ,  200000000, 200,  6, 3, 28),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {

	PLL_4600_RATE(192000000, 48, 3, 1,     0, 0),

	PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),

	PLL_4600_RATE(180000000, 45, 3, 1,     0, 0),

	PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),

	PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),

	PLL_4600_RATE( 49151992, 49, 3, 3,  9961, 0),

	PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),

	PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1,     0, 0),

	PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),

	PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1,     0, 0),

	PLL_4600_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710, 1),

	PLL_4600_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762, 1),

	PLL_4600_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961, 0),

	PLL_4600_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381, 0),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {

	PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),

	PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1,  1, 1),

	PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),

	PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),

	PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),

	PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),

	PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1,  1, 1),

	PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),

	PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),

	PLL_4650_RATE(24 * MHZ,  55360351, 53, 3, 3, 2417, 0, 17, 0),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {

	PLL_35XX_RATE(1704000000, 213, 3, 0),

	PLL_35XX_RATE(1600000000, 200, 3, 0),

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),

	PLL_35XX_RATE(1200000000, 200, 4, 0),

	PLL_35XX_RATE(1100000000, 275, 6, 0),

	PLL_35XX_RATE(1000000000, 125, 3, 0),

	PLL_35XX_RATE( 900000000, 150, 4, 0),

	PLL_35XX_RATE( 800000000, 100, 3, 0),

	PLL_35XX_RATE( 700000000, 175, 3, 1),

	PLL_35XX_RATE( 600000000, 200, 4, 1),

	PLL_35XX_RATE( 500000000, 125, 3, 1),

	PLL_35XX_RATE( 400000000, 100, 3, 1),

	PLL_35XX_RATE( 300000000, 200, 4, 2),

	PLL_35XX_RATE( 200000000, 100, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),

	PLL_35XX_RATE(24 * MHZ,  900000000, 150, 4, 0),

	PLL_35XX_RATE(24 * MHZ,  800000000, 100, 3, 0),

	PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  600000000, 200, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  500000000, 125, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  400000000, 100, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  300000000, 200, 4, 2),

	PLL_35XX_RATE(24 * MHZ,  200000000, 100, 3, 2),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {

	PLL_36XX_RATE(192000000, 48, 3, 1,     0),

	PLL_36XX_RATE(180633605, 45, 3, 1, 10381),

	PLL_36XX_RATE(180000000, 45, 3, 1,     0),

	PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),

	PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),

	PLL_36XX_RATE( 49151992, 49, 3, 3,  9961),

	PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),

	PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),

	PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),

	PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710),

	PLL_36XX_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762),

	PLL_36XX_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961),

	PLL_36XX_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {

	PLL_36XX_RATE(533000000, 133, 3, 1, 16384),

	PLL_36XX_RATE(440000000, 110, 3, 1,     0),

	PLL_36XX_RATE(350000000, 175, 3, 2,     0),

	PLL_36XX_RATE(266000000, 133, 3, 2,     0),

	PLL_36XX_RATE(160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(106031250,  53, 3, 2,  1024),

	PLL_36XX_RATE( 53015625,  53, 3, 3,  1024),

	PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),

	PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 106031250,  53, 3, 2,  1024),

	PLL_36XX_RATE(24 * MHZ,  53015625,  53, 3, 3,  1024),

	{ /* sentinel */ }

};

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