Commit c5d326c2 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt4-for-v3.15' of... 

Merge tag 'renesas-dt4-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Fourth Round of Renesas ARM Based SoC DT Updates for v3.15" from Simon
Horman:

* r8a7791 (R-Car M2) based koelsch board
  - Add SDHI devices
  - Add ethernet

* r8a7791 (R-Car M2) SoC
  - Correct clock index for i2c5

* r8a7790 (R-Car H2) based lager board
  - Add ethernet

* tag 'renesas-dt4-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: Add SDHI devices for Koelsch DTS
  ARM: shmobile: Add SDHI devices to r8a7791 DTSI
  ARM: shmobile: r8a7791: fix clock index for i2c5
  ARM: shmobile: koelsch: add Ether DT support
  ARM: shmobile: r8a7791: add Ether DT support
  ARM: shmobile: lager: add Ether DT support
  ARM: shmobile: r8a7790: add Ether DT support

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 46d34000 2c60a7df

arch/arm/boot/dts/r8a7790-lager.dts

+27 −1
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the Lager board

 *

 * Copyright (C) 2013 Renesas Solutions Corp.

 * Copyright (C) 2013-2014 Renesas Solutions Corp.

 * Copyright (C) 2014 Cogent Embedded, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -124,6 +125,16 @@ 
		renesas,function = "scif0";

	};



	ether_pins: ether {

		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";

		renesas,function = "eth";

	};



	phy1_pins: phy1 {

		renesas,groups = "intc_irq0";

		renesas,function = "intc";

	};



	scif1_pins: serial1 {

		renesas,groups = "scif1_data";

		renesas,function = "scif1";
@@ -150,6 +161,21 @@ 
	};

};



&ether {

	pinctrl-0 = <&ether_pins &phy1_pins>;

	pinctrl-names = "default";



	phy-handle = <&phy1>;

	renesas,ether-link-active-low;

	status = "ok";



	phy1: ethernet-phy@1 {

		reg = <1>;

		interrupt-parent = <&irqc0>;

		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

	};

};



&mmcif1 {

	pinctrl-0 = <&mmc1_pins>;

	pinctrl-names = "default";

arch/arm/boot/dts/r8a7790.dtsi

+13 −1
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the r8a7790 SoC

 *

 * Copyright (C) 2013 Renesas Solutions Corp.

 * Copyright (C) 2013-2014 Renesas Solutions Corp.

 * Copyright (C) 2014 Cogent Embedded Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -379,6 +380,17 @@ 
		status = "disabled";

	};



	ether: ethernet@ee700000 {

		compatible = "renesas,ether-r8a7790";

		reg = <0 0xee700000 0 0x400>;

		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp8_clks R8A7790_CLK_ETHER>;

		phy-mode = "rmii";

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	sata0: sata@ee300000 {

		compatible = "renesas,sata-r8a7790";

		reg = <0 0xee300000 0 0x2000>;

arch/arm/boot/dts/r8a7791-koelsch.dts

+146 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
 * Device Tree Source for the Koelsch board

 *

 * Copyright (C) 2013 Renesas Electronics Corporation

 * Copyright (C) 2013 Renesas Solutions Corp.

 * Copyright (C) 2013-2014 Renesas Solutions Corp.

 * Copyright (C) 2014 Cogent Embedded, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -102,6 +103,78 @@ 
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;

		};

	};



	vcc_sdhi0: regulator@0 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI0 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi0: regulator@1 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	vcc_sdhi1: regulator@2 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI1 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi1: regulator@3 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI1 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	vcc_sdhi2: regulator@4 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI2 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi2: regulator@5 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI2 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};

};



&extal_clk {
@@ -146,16 +219,88 @@ 
		renesas,function = "scif1";

	};



	ether_pins: ether {

		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";

		renesas,function = "eth";

	};



	phy1_pins: phy1 {

		renesas,groups = "intc_irq0";

		renesas,function = "intc";

	};



	sdhi0_pins: sd0 {

		renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";

		renesas,function = "sdhi0";

	};



	sdhi1_pins: sd1 {

		renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";

		renesas,function = "sdhi1";

	};



	sdhi2_pins: sd2 {

		renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";

		renesas,function = "sdhi2";

	};



	qspi_pins: spi {

		renesas,groups = "qspi_ctrl", "qspi_data4";

		renesas,function = "qspi";

	};

};



&ether {

	pinctrl-0 = <&ether_pins &phy1_pins>;

	pinctrl-names = "default";



	phy-handle = <&phy1>;

	renesas,ether-link-active-low;

	status = "ok";



	phy1: ethernet-phy@1 {

		reg = <1>;

		interrupt-parent = <&irqc0>;

		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

	};

};



&sata0 {

	status = "okay";

};



&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;

	status = "okay";

};



&sdhi1 {

	pinctrl-0 = <&sdhi1_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi1>;

	vqmmc-supply = <&vccq_sdhi1>;

	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;

	status = "okay";

};



&sdhi2 {

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi2>;

	vqmmc-supply = <&vccq_sdhi2>;

	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&spi {

	pinctrl-0 = <&qspi_pins>;

	pinctrl-names = "default";

arch/arm/boot/dts/r8a7791.dtsi

+41 −2
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
 * Device Tree Source for the r8a7791 SoC

 *

 * Copyright (C) 2013 Renesas Electronics Corporation

 * Copyright (C) 2013 Renesas Solutions Corp.

 * Copyright (C) 2013-2014 Renesas Solutions Corp.

 * Copyright (C) 2014 Cogent Embedded Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -245,6 +246,33 @@ 
		#gpio-range-cells = <3>;

	};



	sdhi0: sd@ee100000 {

		compatible = "renesas,sdhi-r8a7791";

		reg = <0 0xee100000 0 0x200>;

		interrupt-parent = <&gic>;

		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;

		status = "disabled";

	};



	sdhi1: sd@ee140000 {

		compatible = "renesas,sdhi-r8a7791";

		reg = <0 0xee140000 0 0x100>;

		interrupt-parent = <&gic>;

		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;

		status = "disabled";

	};



	sdhi2: sd@ee160000 {

		compatible = "renesas,sdhi-r8a7791";

		reg = <0 0xee160000 0 0x100>;

		interrupt-parent = <&gic>;

		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;

		status = "disabled";

	};



	scifa0: serial@e6c40000 {

		compatible = "renesas,scifa-r8a7791", "renesas,scifa";

		reg = <0 0xe6c40000 0 64>;
@@ -407,6 +435,17 @@ 
		status = "disabled";

	};



	ether: ethernet@ee700000 {

		compatible = "renesas,ether-r8a7791";

		reg = <0 0xee700000 0 0x400>;

		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;

		phy-mode = "rmii";

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	sata0: sata@ee300000 {

		compatible = "renesas,sata-r8a7791";

		reg = <0 0xee300000 0 0x2000>;
@@ -731,7 +770,7 @@ 
			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD

				R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3

				R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3

				R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0

			>;

			clock-output-names =

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