Commit c1079b4e authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
Browse files

clk: qcom: dispcc: Add support for display port clocks 



SDM845 dispcc supports RCG and CBCRs for display port, so add support for
the same.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190731182713.8123-3-tdas@codeaurora.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent cddf1f82

drivers/clk/qcom/dispcc-sdm845.c

+213 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -29,6 +29,8 @@ enum { 
	P_DSI1_PHY_PLL_OUT_DSICLK,

	P_GPLL0_OUT_MAIN,

	P_GPLL0_OUT_MAIN_DIV,

	P_DP_PHY_PLL_LINK_CLK,

	P_DP_PHY_PLL_VCO_DIV_CLK,

};



static const struct parent_map disp_cc_parent_map_0[] = {
@@ -45,6 +47,20 @@ static const char * const disp_cc_parent_names_0[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_DP_PHY_PLL_LINK_CLK, 1 },

	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const disp_cc_parent_names_1[] = {

	"bi_tcxo",

	"dp_link_clk_divsel_ten",

	"dp_vco_divided_clk_src_mux",

	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_2[] = {

	{ P_BI_TCXO, 0 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },
@@ -128,6 +144,81 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 
	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {

	.cmd_rcgr = 0x219c,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_2,

	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_aux_clk_src",

		.parent_names = disp_cc_parent_names_2,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

};



static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {

	.cmd_rcgr = 0x2154,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_crypto_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.ops = &clk_byte2_ops,

	},

};



static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {

	.cmd_rcgr = 0x2138,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_link_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

	},

};



static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {

	.cmd_rcgr = 0x2184,

	.mnd_width = 16,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_pixel1_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_dp_ops,

	},

};



static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {

	.cmd_rcgr = 0x216c,

	.mnd_width = 16,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_pixel_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_dp_ops,

	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }
@@ -391,6 +482,114 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 
	},

};



static struct clk_branch disp_cc_mdss_dp_aux_clk = {

	.halt_reg = 0x2054,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2054,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_aux_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_aux_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_dp_crypto_clk = {

	.halt_reg = 0x2048,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2048,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_crypto_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_crypto_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_dp_link_clk = {

	.halt_reg = 0x2040,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2040,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_link_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_link_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */

static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {

	.halt_reg = 0x2044,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2044,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_link_intf_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_link_clk_src",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {

	.halt_reg = 0x2050,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2050,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_pixel1_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_pixel1_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_dp_pixel_clk = {

	.halt_reg = 0x204c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x204c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_pixel_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_pixel_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_esc0_clk = {

	.halt_reg = 0x2038,

	.halt_check = BRANCH_HALT,
@@ -589,6 +788,19 @@ static struct clk_regmap *disp_cc_sdm845_clocks[] = { 
	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,

	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =

					&disp_cc_mdss_byte1_div_clk_src.clkr,

	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,

	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,

	[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,

	[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =

					&disp_cc_mdss_dp_crypto_clk_src.clkr,

	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,

	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,

	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,

	[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,

	[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =

					&disp_cc_mdss_dp_pixel1_clk_src.clkr,

	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,

	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,

	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,

	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,

	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,

include/dt-bindings/clock/qcom,dispcc-sdm845.h

+12 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
@@ -35,6 +35,17 @@ 
#define DISP_CC_PLL0						25

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27

#define DISP_CC_MDSS_DP_AUX_CLK					28

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				29

#define DISP_CC_MDSS_DP_CRYPTO_CLK				30

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				31

#define DISP_CC_MDSS_DP_LINK_CLK				32

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				33

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				34

#define DISP_CC_MDSS_DP_PIXEL1_CLK				35

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				36

#define DISP_CC_MDSS_DP_PIXEL_CLK				37

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				38



/* DISP_CC Reset */

#define DISP_CC_MDSS_RSCC_BCR					0

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