clk: qcom: rcg2: Add support for display port clock ops (cddf1f82) · Commits · 戴 / test

drivers/clk/qcom/Kconfig

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Original line number	Diff line number	Diff line
		@@ -14,6 +14,7 @@ menuconfig COMMON_CLK_QCOM
		tristate "Support for Qualcomm's clock controllers"
		depends on OF
		depends on ARCH_QCOM \|\| COMPILE_TEST
		select RATIONAL
		select REGMAP_MMIO
		select RESET_CONTROLLER

drivers/clk/qcom/clk-rcg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -161,6 +161,7 @@ extern const struct clk_ops clk_byte2_ops;
		extern const struct clk_ops clk_pixel_ops;
		extern const struct clk_ops clk_gfx3d_ops;
		extern const struct clk_ops clk_rcg2_shared_ops;
		extern const struct clk_ops clk_dp_ops;

		struct clk_rcg_dfs_data {
		struct clk_rcg2 *rcg;

drivers/clk/qcom/clk-rcg2.c

+77 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@
		#include <linux/export.h>
		#include <linux/clk-provider.h>
		#include <linux/delay.h>
		#include <linux/rational.h>
		#include <linux/regmap.h>
		#include <linux/math64.h>
		#include <linux/slab.h>
		@@ -1124,3 +1125,79 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,
		return 0;
		}
		EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);

		static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		struct freq_tbl f = { 0 };
		u32 mask = BIT(rcg->hid_width) - 1;
		u32 hid_div, cfg;
		int i, num_parents = clk_hw_get_num_parents(hw);
		unsigned long num, den;

		rational_best_approximation(parent_rate, rate,
		GENMASK(rcg->mnd_width - 1, 0),
		GENMASK(rcg->mnd_width - 1, 0), &den, &num);

		if (!num \|\| !den)
		return -EINVAL;

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
		hid_div = cfg;
		cfg &= CFG_SRC_SEL_MASK;
		cfg >>= CFG_SRC_SEL_SHIFT;

		for (i = 0; i < num_parents; i++) {
		if (cfg == rcg->parent_map[i].cfg) {
		f.src = rcg->parent_map[i].src;
		break;
		}
		}

		f.pre_div = hid_div;
		f.pre_div >>= CFG_SRC_DIV_SHIFT;
		f.pre_div &= mask;

		if (num != den) {
		f.m = num;
		f.n = den;
		} else {
		f.m = 0;
		f.n = 0;
		}

		return clk_rcg2_configure(rcg, &f);
		}

		static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
		{
		return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
		}

		static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
		{
		struct clk_rate_request parent_req = *req;
		int ret;

		ret = __clk_determine_rate(clk_hw_get_parent(hw), &parent_req);
		if (ret)
		return ret;

		req->best_parent_rate = parent_req.rate;

		return 0;
		}

		const struct clk_ops clk_dp_ops = {
		.is_enabled = clk_rcg2_is_enabled,
		.get_parent = clk_rcg2_get_parent,
		.set_parent = clk_rcg2_set_parent,
		.recalc_rate = clk_rcg2_recalc_rate,
		.set_rate = clk_rcg2_dp_set_rate,
		.set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
		.determine_rate = clk_rcg2_dp_determine_rate,
		};
		EXPORT_SYMBOL_GPL(clk_dp_ops);

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