arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux (b766e3b0) · Commits · 戴 / test

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

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		@@ -5,6 +5,8 @@
		* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
		*/
		#include <dt-bindings/phy/phy.h>
		#include <dt-bindings/mux/mux.h>
		#include <dt-bindings/mux/mux-j721e-wiz.h>

		&cbass_main {
		msmc_ram: sram@70000000 {
		@@ -19,6 +21,31 @@
		};
		};

		scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: serdes-ln-ctrl@4080 {
		compatible = "mmio-mux";
		reg = <0x00004080 0x50>;
		#mux-control-cells = <1>;
		mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
		<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
		<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
		<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
		<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
		/* SERDES4 lane0/1/2/3 select */
		idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
		<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
		<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
		<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
		<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
		};
		};

		gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;

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		/* SPDX-License-Identifier: GPL-2.0 */
		/*
		* This header provides constants for J721E WIZ.
		*/

		#ifndef _DT_BINDINGS_J721E_WIZ
		#define _DT_BINDINGS_J721E_WIZ

		#define SERDES0_LANE0_QSGMII_LANE1 0x0
		#define SERDES0_LANE0_PCIE0_LANE0 0x1
		#define SERDES0_LANE0_USB3_0_SWAP 0x2

		#define SERDES0_LANE1_QSGMII_LANE2 0x0
		#define SERDES0_LANE1_PCIE0_LANE1 0x1
		#define SERDES0_LANE1_USB3_0 0x2

		#define SERDES1_LANE0_QSGMII_LANE3 0x0
		#define SERDES1_LANE0_PCIE1_LANE0 0x1
		#define SERDES1_LANE0_USB3_1_SWAP 0x2
		#define SERDES1_LANE0_SGMII_LANE0 0x3

		#define SERDES1_LANE1_QSGMII_LANE4 0x0
		#define SERDES1_LANE1_PCIE1_LANE1 0x1
		#define SERDES1_LANE1_USB3_1 0x2
		#define SERDES1_LANE1_SGMII_LANE1 0x3

		#define SERDES2_LANE0_PCIE2_LANE0 0x1
		#define SERDES2_LANE0_SGMII_LANE0 0x3
		#define SERDES2_LANE0_USB3_1_SWAP 0x2

		#define SERDES2_LANE1_PCIE2_LANE1 0x1
		#define SERDES2_LANE1_USB3_1 0x2
		#define SERDES2_LANE1_SGMII_LANE1 0x3

		#define SERDES3_LANE0_PCIE3_LANE0 0x1
		#define SERDES3_LANE0_USB3_0_SWAP 0x2

		#define SERDES3_LANE1_PCIE3_LANE1 0x1
		#define SERDES3_LANE1_USB3_0 0x2

		#define SERDES4_LANE0_EDP_LANE0 0x0
		#define SERDES4_LANE0_QSGMII_LANE5 0x2

		#define SERDES4_LANE1_EDP_LANE1 0x0
		#define SERDES4_LANE1_QSGMII_LANE6 0x2

		#define SERDES4_LANE2_EDP_LANE2 0x0
		#define SERDES4_LANE2_QSGMII_LANE7 0x2

		#define SERDES4_LANE3_EDP_LANE3 0x0
		#define SERDES4_LANE3_QSGMII_LANE8 0x2

		#endif /* _DT_BINDINGS_J721E_WIZ */