Commit afd094eb authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tero Kristo
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arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes 



Add DT nodes for all instances of WIZ and SERDES modules.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent e0f94691

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+241 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 *

 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/

 */

#include <dt-bindings/phy/phy.h>



&cbass_main {

	msmc_ram: sram@70000000 {
@@ -277,6 +278,246 @@ 
		pinctrl-single,function-mask = <0xffffffff>;

	};



	dummy_cmn_refclk: dummy-cmn-refclk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <100000000>;

	};



	dummy_cmn_refclk1: dummy-cmn-refclk1 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <100000000>;

	};



	serdes_wiz0: wiz@5000000 {

		compatible = "ti,j721e-wiz-16g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;

		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;

		num-lanes = <2>;

		#reset-cells = <1>;

		ranges = <0x5000000 0x0 0x5000000 0x10000>;



		wiz0_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 292 11>;

		};



		wiz0_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 292 0>;

		};



		wiz0_refclk_dig: refclk-dig {

			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_refclk_dig>;

			assigned-clock-parents = <&k3_clks 292 11>;

		};



		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {

			clocks = <&wiz0_refclk_dig>;

			#clock-cells = <0>;

		};



		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {

			clocks = <&wiz0_pll1_refclk>;

			#clock-cells = <0>;

		};



		serdes0: serdes@5000000 {

			compatible = "ti,sierra-phy-t0";

			reg-names = "serdes";

			reg = <0x5000000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&serdes_wiz0 0>;

			reset-names = "sierra_reset";

			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;

			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";

		};

	};



	serdes_wiz1: wiz@5010000 {

		compatible = "ti,j721e-wiz-16g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;

		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;

		num-lanes = <2>;

		#reset-cells = <1>;

		ranges = <0x5010000 0x0 0x5010000 0x10000>;



		wiz1_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz1_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 293 13>;

		};



		wiz1_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz1_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 293 0>;

		};



		wiz1_refclk_dig: refclk-dig {

			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz1_refclk_dig>;

			assigned-clock-parents = <&k3_clks 293 13>;

		};



		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{

			clocks = <&wiz1_refclk_dig>;

			#clock-cells = <0>;

		};



		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {

			clocks = <&wiz1_pll1_refclk>;

			#clock-cells = <0>;

		};



		serdes1: serdes@5010000 {

			compatible = "ti,sierra-phy-t0";

			reg-names = "serdes";

			reg = <0x5010000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&serdes_wiz1 0>;

			reset-names = "sierra_reset";

			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;

			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";

		};

	};



	serdes_wiz2: wiz@5020000 {

		compatible = "ti,j721e-wiz-16g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;

		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;

		num-lanes = <2>;

		#reset-cells = <1>;

		ranges = <0x5020000 0x0 0x5020000 0x10000>;



		wiz2_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz2_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 294 11>;

		};



		wiz2_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz2_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 294 0>;

		};



		wiz2_refclk_dig: refclk-dig {

			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz2_refclk_dig>;

			assigned-clock-parents = <&k3_clks 294 11>;

		};



		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {

			clocks = <&wiz2_refclk_dig>;

			#clock-cells = <0>;

		};



		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {

			clocks = <&wiz2_pll1_refclk>;

			#clock-cells = <0>;

		};



		serdes2: serdes@5020000 {

			compatible = "ti,sierra-phy-t0";

			reg-names = "serdes";

			reg = <0x5020000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&serdes_wiz2 0>;

			reset-names = "sierra_reset";

			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;

			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";

		};

	};



	serdes_wiz3: wiz@5030000 {

		compatible = "ti,j721e-wiz-16g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;

		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;

		num-lanes = <2>;

		#reset-cells = <1>;

		ranges = <0x5030000 0x0 0x5030000 0x10000>;



		wiz3_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz3_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 295 9>;

		};



		wiz3_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz3_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 295 0>;

		};



		wiz3_refclk_dig: refclk-dig {

			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;

			#clock-cells = <0>;

			assigned-clocks = <&wiz3_refclk_dig>;

			assigned-clock-parents = <&k3_clks 295 9>;

		};



		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {

			clocks = <&wiz3_refclk_dig>;

			#clock-cells = <0>;

		};



		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {

			clocks = <&wiz3_pll1_refclk>;

			#clock-cells = <0>;

		};



		serdes3: serdes@5030000 {

			compatible = "ti,sierra-phy-t0";

			reg-names = "serdes";

			reg = <0x5030000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&serdes_wiz3 0>;

			reset-names = "sierra_reset";

			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;

			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";

		};

	};



	main_uart0: serial@2800000 {

		compatible = "ti,j721e-uart", "ti,am654-uart";

		reg = <0x00 0x02800000 0x00 0x100>;

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