Commit b6bb2bc2 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu'...

Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next

 - Add support to get duty cycle of generic pwm clks

* clk-pwm-duty:
  clk: pwm: implement the .get_duty_cycle callback

* clk-bcm:
  clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB
  clk: bcm: Make BCM2835 clock drivers selectable

* clk-mtk:
  clk: mediatek: Remove MT8183 unused clock
  clk: mediatek: add audsys clock driver for MT8516
  dt-bindings: mediatek: audsys: add support for MT8516

* clk-qcom-msm8998-gpu:
  dt-bindings: clock: Document gpucc for msm8998

* clk-renesas:
  clk: renesas: cpg-mssr: Use [] to denote a flexible array member
  clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
  clk: renesas: mstp: Combine group-private and clock array allocation
  clk: renesas: div6: Combine clock-private and parent array allocation
  clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
  clk: renesas: r8a774a1: Add TMU clock
  clk: renesas: r8a77995: Add CMM clocks
  clk: renesas: r8a77990: Add CMM clocks
  clk: renesas: r8a77965: Add CMM clocks
  clk: renesas: r8a7795: Add CMM clocks
  clk: renesas: r9a06g032: Add clock domain support
  dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
  clk: renesas: mstp: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
  clk: renesas: r8a7796: Add CMM clocks
  clk: renesas: r8a779{5|6|65}: Add TPU clock
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+1 −0
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@@ -10,6 +10,7 @@ Required Properties:
	- "mediatek,mt7622-audsys", "syscon"
	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
	- "mediatek,mt8183-audiosys", "syscon"
	- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1

The AUDSYS controller uses the common clk binding from
+3 −1
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@@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding
--------------------------------------------------

Required properties :
- compatible : shall contain "qcom,sdm845-gpucc"
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
- reg : shall contain base register location and length
- #clock-cells : from common clock binding, shall contain 1
- #reset-cells : from common reset binding, shall contain 1
- #power-domain-cells : from generic power domain binding, shall contain 1
- clocks : shall contain the XO clock
	   shall contain the gpll0 out main clock (msm8998)
- clock-names : shall be "xo"
		shall be "gpll0" (msm8998)

Example:
	gpucc: clock-controller@5090000 {
+5 −2
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required Properties:
	- external (optional) RGMII_REFCLK
  - clock-names: Must be:
        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
  - #power-domain-cells: Must be 0

Examples
--------
@@ -27,6 +28,7 @@ Examples
		clocks = <&ext_mclk>, <&ext_rtc_clk>,
				<&ext_jtag_clk>, <&ext_rgmii_ref>;
		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
		#power-domain-cells = <0>;
	};

  - Other nodes can use the clocks provided by SYSCTRL as in:
@@ -38,6 +40,7 @@ Examples
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&sysctrl R9A06G032_CLK_UART0>;
		clock-names = "baudclk";
		clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		power-domains = <&sysctrl>;
	};
+9 −0
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config CLK_BCM2835
	bool "Broadcom BCM2835 clock support"
	depends on ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST
	depends on COMMON_CLK
	default ARCH_BCM2835 || ARCH_BRCMSTB
	help
	  Enable common clock framework support for Broadcom BCM2835
	  SoCs.

config CLK_BCM_63XX
	bool "Broadcom BCM63xx clock support"
	depends on ARCH_BCM_63XX || COMPILE_TEST
+2 −2
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@@ -5,8 +5,8 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC)	+= clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835-aux.o
obj-$(CONFIG_CLK_BCM2835)	+= clk-bcm2835.o
obj-$(CONFIG_CLK_BCM2835)	+= clk-bcm2835-aux.o
obj-$(CONFIG_ARCH_BCM_53573)	+= clk-bcm53573-ilp.o
obj-$(CONFIG_CLK_BCM_CYGNUS)	+= clk-cygnus.o
obj-$(CONFIG_CLK_BCM_HR2)	+= clk-hr2.o
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