Commit 5b68f22c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.3-tag2' of... 

Merge tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add CMM (Color Management Module) clocks on R-Car H3, M3-N, E3, and D3
  - Add TPU (Timer Pulse Unit / PWM) clocks on RZ/G2M
  - Small cleanups and fixes

* tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Use [] to denote a flexible array member
  clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
  clk: renesas: mstp: Combine group-private and clock array allocation
  clk: renesas: div6: Combine clock-private and parent array allocation
  clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
  clk: renesas: r8a774a1: Add TMU clock
  clk: renesas: r8a77995: Add CMM clocks
  clk: renesas: r8a77990: Add CMM clocks
  clk: renesas: r8a77965: Add CMM clocks
  clk: renesas: r8a7795: Add CMM clocks
parents f81d0860 ec2b827b

drivers/clk/renesas/clk-div6.c

+5 −14
Original line number Diff line number Diff line
@@ -30,8 +30,8 @@ 
 * @div: divisor value (1-64)

 * @src_shift: Shift to access the register bits to select the parent clock

 * @src_width: Number of register bits to select the parent clock (may be 0)

 * @parents: Array to map from valid parent clocks indices to hardware indices

 * @nb: Notifier block to save/restore clock state for system resume

 * @parents: Array to map from valid parent clocks indices to hardware indices

 */

struct div6_clock {

	struct clk_hw hw;
@@ -39,8 +39,8 @@ struct div6_clock { 
	unsigned int div;

	u32 src_shift;

	u32 src_width;

	u8 *parents;

	struct notifier_block nb;

	u8 parents[];

};



#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
@@ -221,17 +221,10 @@ struct clk * __init cpg_div6_register(const char *name, 
	struct clk *clk;

	unsigned int i;



	clock = kzalloc(sizeof(*clock), GFP_KERNEL);

	clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);

	if (!clock)

		return ERR_PTR(-ENOMEM);



	clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),

				       GFP_KERNEL);

	if (!clock->parents) {

		clk = ERR_PTR(-ENOMEM);

		goto free_clock;

	}



	clock->reg = reg;



	/*
@@ -259,7 +252,7 @@ struct clk * __init cpg_div6_register(const char *name, 
		pr_err("%s: invalid number of parents for DIV6 clock %s\n",

		       __func__, name);

		clk = ERR_PTR(-EINVAL);

		goto free_parents;

		goto free_clock;

	}



	/* Filter out invalid parents */
@@ -282,7 +275,7 @@ struct clk * __init cpg_div6_register(const char *name, 


	clk = clk_register(NULL, &clock->hw);

	if (IS_ERR(clk))

		goto free_parents;

		goto free_clock;



	if (notifiers) {

		clock->nb.notifier_call = cpg_div6_clock_notifier_call;
@@ -291,8 +284,6 @@ struct clk * __init cpg_div6_register(const char *name, 


	return clk;



free_parents:

	kfree(clock->parents);

free_clock:

	kfree(clock);

	return clk;

drivers/clk/renesas/clk-mstp.c

+6 −6
Original line number Diff line number Diff line
@@ -30,11 +30,12 @@ 
/**

 * struct mstp_clock_group - MSTP gating clocks group

 *

 * @data: clocks in this group

 * @data: clock specifier translation for clocks in this group

 * @smstpcr: module stop control register

 * @mstpsr: module stop status register (optional)

 * @lock: protects writes to SMSTPCR

 * @width_8bit: registers are 8-bit, not 32-bit

 * @clks: clocks in this group

 */

struct mstp_clock_group {

	struct clk_onecell_data data;
@@ -42,6 +43,7 @@ struct mstp_clock_group { 
	void __iomem *mstpsr;

	spinlock_t lock;

	bool width_8bit;

	struct clk *clks[];

};



/**
@@ -186,14 +188,13 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) 
	struct clk **clks;

	unsigned int i;



	group = kzalloc(sizeof(*group), GFP_KERNEL);

	clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);

	if (group == NULL || clks == NULL) {

	group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);

	if (group == NULL) {

		kfree(group);

		kfree(clks);

		return;

	}



	clks = group->clks;

	spin_lock_init(&group->lock);

	group->data.clks = clks;
@@ -203,7 +204,6 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) 
	if (group->smstpcr == NULL) {

		pr_err("%s: failed to remap SMSTPCR\n", __func__);

		kfree(group);

		kfree(clks);

		return;

	}

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+5 −0
Original line number Diff line number Diff line
@@ -113,6 +113,11 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {

	DEF_MOD("tmu4",			 121,	R8A774A1_CLK_S0D6),

	DEF_MOD("tmu3",			 122,	R8A774A1_CLK_S3D2),

	DEF_MOD("tmu2",			 123,	R8A774A1_CLK_S3D2),

	DEF_MOD("tmu1",			 124,	R8A774A1_CLK_S3D2),

	DEF_MOD("tmu0",			 125,	R8A774A1_CLK_CP),

	DEF_MOD("fdp1-0",		 119,	R8A774A1_CLK_S0D1),

	DEF_MOD("scif5",		 202,	R8A774A1_CLK_S3D4),

	DEF_MOD("scif4",		 203,	R8A774A1_CLK_S3D4),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -202,6 +202,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D2),

	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D2),

	DEF_MOD("cmm3",			 708,	R8A7795_CLK_S2D1),

	DEF_MOD("cmm2",			 709,	R8A7795_CLK_S2D1),

	DEF_MOD("cmm1",			 710,	R8A7795_CLK_S2D1),

	DEF_MOD("cmm0",			 711,	R8A7795_CLK_S2D1),

	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */

	DEF_MOD("csi20",		 714,	R8A7795_CLK_CSI0),

	DEF_MOD("csi41",		 715,	R8A7795_CLK_CSI0),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+3 −0
Original line number Diff line number Diff line
@@ -180,6 +180,9 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D2),

	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D2),

	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D2),

	DEF_MOD("cmm3",			708,	R8A77965_CLK_S2D1),

	DEF_MOD("cmm1",			710,	R8A77965_CLK_S2D1),

	DEF_MOD("cmm0",			711,	R8A77965_CLK_S2D1),

	DEF_MOD("csi20",		714,	R8A77965_CLK_CSI0),

	DEF_MOD("csi40",		716,	R8A77965_CLK_CSI0),

	DEF_MOD("du3",			721,	R8A77965_CLK_S2D1),

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