Commit f81d0860 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.3-tag1' of... 

Merge tag 'clk-renesas-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add TPU (Timer Pulse Unit / PWM) clocks on R-Car H3, M3-W, and M3-N
  - Add CMM (Color Management Module) clocks on R-Car M3-W
  - Add Clock Domain support on RZ/N1

* tag 'clk-renesas-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a06g032: Add clock domain support
  dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
  clk: renesas: mstp: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
  clk: renesas: r8a7796: Add CMM clocks
  clk: renesas: r8a779{5|6|65}: Add TPU clock
parents a188339c aad03a66

Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt

+5 −2
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required Properties: 
	- external (optional) RGMII_REFCLK

  - clock-names: Must be:

        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

  - #power-domain-cells: Must be 0



Examples

--------
@@ -27,6 +28,7 @@ Examples 
		clocks = <&ext_mclk>, <&ext_rtc_clk>,

				<&ext_jtag_clk>, <&ext_rgmii_ref>;

		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

		#power-domain-cells = <0>;

	};



  - Other nodes can use the clocks provided by SYSCTRL as in:
@@ -38,6 +40,7 @@ Examples 
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&sysctrl R9A06G032_CLK_UART0>;

		clock-names = "baudclk";

		clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;

		clock-names = "baudclk", "apb_pclk";

		power-domains = <&sysctrl>;

	};

drivers/clk/renesas/clk-mstp.c

+2 −6
Original line number Diff line number Diff line
@@ -297,16 +297,12 @@ found: 
		return PTR_ERR(clk);



	error = pm_clk_create(dev);

	if (error) {

		dev_err(dev, "pm_clk_create failed %d\n", error);

	if (error)

		goto fail_put;

	}



	error = pm_clk_add_clk(dev, clk);

	if (error) {

		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);

	if (error)

		goto fail_destroy;

	}



	return 0;

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),

	DEF_MOD("cmt0",			 303,	R8A7795_CLK_R),

	DEF_MOD("tpu0",			 304,	R8A7795_CLK_S3D4),

	DEF_MOD("scif2",		 310,	R8A7795_CLK_S3D4),

	DEF_MOD("sdif3",		 311,	R8A7795_CLK_SD3),

	DEF_MOD("sdif2",		 312,	R8A7795_CLK_SD2),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7796_CLK_R),

	DEF_MOD("cmt0",			 303,	R8A7796_CLK_R),

	DEF_MOD("tpu0",			 304,	R8A7796_CLK_S3D4),

	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),

	DEF_MOD("sdif3",		 311,	R8A7796_CLK_SD3),

	DEF_MOD("sdif2",		 312,	R8A7796_CLK_SD2),
@@ -180,6 +181,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("ehci1",		 702,	R8A7796_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A7796_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7796_CLK_S3D2),

	DEF_MOD("cmm2",			 709,	R8A7796_CLK_S2D1),

	DEF_MOD("cmm1",			 710,	R8A7796_CLK_S2D1),

	DEF_MOD("cmm0",			 711,	R8A7796_CLK_S2D1),

	DEF_MOD("csi20",		 714,	R8A7796_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A7796_CLK_CSI0),

	DEF_MOD("du2",			 722,	R8A7796_CLK_S2D1),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("cmt2",			301,	R8A77965_CLK_R),

	DEF_MOD("cmt1",			302,	R8A77965_CLK_R),

	DEF_MOD("cmt0",			303,	R8A77965_CLK_R),

	DEF_MOD("tpu0",			304,	R8A77965_CLK_S3D4),

	DEF_MOD("scif2",		310,	R8A77965_CLK_S3D4),

	DEF_MOD("sdif3",		311,	R8A77965_CLK_SD3),

	DEF_MOD("sdif2",		312,	R8A77965_CLK_SD2),

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