Commit b69fa361 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/icl: Cleanup combo PHY aux power well handlers 



Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.

v2: Don't try to use intel_uncore_rmw for register updates yet; there's
    pending display uncore patches that need to land first.  (Lucas)

v3: Drop the combo phy assertion.  It was backward before, but doesn't
    seem terribly necessary.  I'm keeping the IS_ICELAKE assertion
    though since we often copy/paste/modify the power well tables when
    defining new platforms and it's too easy to cargo cult the
    ICL-specific handling to new platforms that shouldn't use it.
    (Lucas)

v4: Fix build; forgot to commit all the changes.  (CI)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191213010600.701315-1-matthew.d.roper@intel.com


Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent ab340258

drivers/gpu/drm/i915/display/intel_display_power.c

+8 −13
Original line number Original line Diff line number Diff line
@@ -418,7 +418,8 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 
	int pw_idx = power_well->desc->hsw.idx;

	int pw_idx = power_well->desc->hsw.idx;

	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);

	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);

	u32 val;

	u32 val;

	int wa_idx_max;



	WARN_ON(!IS_ICELAKE(dev_priv));





	val = I915_READ(regs->driver);

	val = I915_READ(regs->driver);

	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));

	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -430,14 +431,8 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 




	hsw_wait_for_power_well_enable(dev_priv, power_well);

	hsw_wait_for_power_well_enable(dev_priv, power_well);





	/* Display WA #1178: icl, tgl */

	/* Display WA #1178: icl */

	if (IS_TIGERLAKE(dev_priv))

	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&

		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;

	else

		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;



	if (!IS_ELKHARTLAKE(dev_priv) &&

	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&

	    !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {

	    !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {

		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));

		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));

		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;

		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
@@ -454,10 +449,10 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 
	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);

	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);

	u32 val;

	u32 val;





	if (INTEL_GEN(dev_priv) < 12) {

	WARN_ON(!IS_ICELAKE(dev_priv));



	val = I915_READ(ICL_PORT_CL_DW12(phy));

	val = I915_READ(ICL_PORT_CL_DW12(phy));

	I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);

	I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);

	}





	val = I915_READ(regs->driver);

	val = I915_READ(regs->driver);

	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));

	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));

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