Commit ab340258 authored by Matt Roper's avatar Matt Roper
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drm/i915/tgl: Drop Wa#1178

The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it.  In fact Swati just discovered that applying this workaround
is the root cause of some power well enable failures we've been seeing
in CI (gitlab issue 498).

Once we stop applying this WA, TGL no longer utilizes any of the special
handling provided by icl_combo_phy_aux_power_well_ops so we can just
drop back to using the standard hsw-style power well ops instead.

v3: Drop now-unused _TGL_AUX_ANAOVRD1_C definition too.  (Lucas)

Closes: https://gitlab.freedesktop.org/drm/intel/issues/498


Fixes: deea06b4 ("drm/i915/tgl: apply Display WA #1178 to fix type C dongles")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191213001511.678070-3-matthew.d.roper@intel.com
parent e8ab8d66
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+3 −3
Original line number Diff line number Diff line
@@ -3977,7 +3977,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
	{
		.name = "AUX A",
		.domains = TGL_AUX_A_IO_POWER_DOMAINS,
		.ops = &icl_combo_phy_aux_power_well_ops,
		.ops = &hsw_power_well_ops,
		.id = DISP_PW_ID_NONE,
		{
			.hsw.regs = &icl_aux_power_well_regs,
@@ -3987,7 +3987,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
	{
		.name = "AUX B",
		.domains = TGL_AUX_B_IO_POWER_DOMAINS,
		.ops = &icl_combo_phy_aux_power_well_ops,
		.ops = &hsw_power_well_ops,
		.id = DISP_PW_ID_NONE,
		{
			.hsw.regs = &icl_aux_power_well_regs,
@@ -3997,7 +3997,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
	{
		.name = "AUX C",
		.domains = TGL_AUX_C_IO_POWER_DOMAINS,
		.ops = &icl_combo_phy_aux_power_well_ops,
		.ops = &hsw_power_well_ops,
		.id = DISP_PW_ID_NONE,
		{
			.hsw.regs = &icl_aux_power_well_regs,
+1 −3
Original line number Diff line number Diff line
@@ -9437,11 +9437,9 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A		0x162398
#define _ICL_AUX_ANAOVRD1_B		0x6C398
#define _TGL_AUX_ANAOVRD1_C		0x160398
#define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
						    _ICL_AUX_ANAOVRD1_A, \
						    _ICL_AUX_ANAOVRD1_B, \
						    _TGL_AUX_ANAOVRD1_C))
						    _ICL_AUX_ANAOVRD1_B))
#define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
#define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)