Commit e8ab8d66 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/ehl: Define EHL powerwells independently of ICL 



Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL.  And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is actually necessary for this platform:
 * EHL/JSL don't actually need to program PORT_CL_DW12
 * Display WA #1178 does not apply to EHL/JSL

Thus we can simply drop back to using our standard "hsw-style" power
well ops for EHL AUX power wells.

Bspec: 4301
Fixes: f722b8c1 ("drm/i915/ehl: All EHL ports are combo phys")
Cc: Jose Souza <jose.souza@intel.com>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191213001511.678070-2-matthew.d.roper@intel.com


Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 86ca2bf2

drivers/gpu/drm/i915/display/intel_display_power.c

+147 −0
Original line number Diff line number Diff line
@@ -3688,6 +3688,151 @@ static const struct i915_power_well_desc icl_power_wells[] = { 
	},

};



static const struct i915_power_well_desc ehl_power_wells[] = {

	{

		.name = "always-on",

		.always_on = true,

		.domains = POWER_DOMAIN_MASK,

		.ops = &i9xx_always_on_power_well_ops,

		.id = DISP_PW_ID_NONE,

	},

	{

		.name = "power well 1",

		/* Handled by the DMC firmware */

		.always_on = true,

		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_1,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DC off",

		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",

		.domains = ICL_PW_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_2,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "power well 3",

		.domains = ICL_PW_3_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_3,

			.hsw.irq_pipe_mask = BIT(PIPE_B),

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DDI A IO",

		.domains = ICL_DDI_IO_A_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,

		},

	},

	{

		.name = "DDI B IO",

		.domains = ICL_DDI_IO_B_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,

		},

	},

	{

		.name = "DDI C IO",

		.domains = ICL_DDI_IO_C_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,

		},

	},

	{

		.name = "DDI D IO",

		.domains = ICL_DDI_IO_D_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_D,

		},

	},

	{

		.name = "AUX A",

		.domains = ICL_AUX_A_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,

		},

	},

	{

		.name = "AUX B",

		.domains = ICL_AUX_B_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,

		},

	},

	{

		.name = "AUX C",

		.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,

		},

	},

	{

		.name = "AUX D",

		.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_D,

		},

	},

	{

		.name = "power well 4",

		.domains = ICL_PW_4_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_4,

			.hsw.has_fuses = true,

			.hsw.irq_pipe_mask = BIT(PIPE_C),

		},

	},

};



static const struct i915_power_well_desc tgl_power_wells[] = {

	{

		.name = "always-on",
@@ -4162,6 +4307,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
	 */

	if (IS_GEN(dev_priv, 12)) {

		err = set_power_wells(power_domains, tgl_power_wells);

	} else if (IS_ELKHARTLAKE(dev_priv)) {

		err = set_power_wells(power_domains, ehl_power_wells);

	} else if (IS_GEN(dev_priv, 11)) {

		err = set_power_wells(power_domains, icl_power_wells);

	} else if (IS_CANNONLAKE(dev_priv)) {

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