Commit b612a857 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'next/soc' into next/multiplatform 



* next/soc: (50 commits)
  ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move
  MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
  ARM: bcm2835: instantiate console UART
  ARM: bcm2835: add stub clock driver
  ARM: bcm2835: add system timer
  ARM: bcm2835: add interrupt controller driver
  ARM: add infra-structure for BCM2835 and Raspberry Pi
  ARM: tegra20: add CPU hotplug support
  ARM: tegra30: add CPU hotplug support
  ARM: tegra: clean up the common assembly macros into sleep.h
  ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
  ARM: tegra: introduce tegra_cpu_car_ops structures
  ARM: Tegra: Add smp_twd clock for Tegra20
  ARM: AM33XX: clock: Add dcan clock aliases for device-tree
  ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
  ARM: OMAP: omap_device: idle devices with no driver bound
  ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
  ARM: OMAP: omap_device: keep track of driver bound status
  ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
  ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework
  ...

Change/remove conflict in arch/arm/mach-ux500/clock.c resolved.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ea832c41 3aec092e

Documentation/devicetree/bindings/arm/bcm2835.txt

0 → 100644
+8 −0
Original line number Diff line number Diff line 
Broadcom BCM2835 device tree bindings

-------------------------------------------



Boards with the BCM2835 SoC shall have the following properties:



Required root node property:



compatible = "brcm,bcm2835";

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

0 → 100644
+110 −0
Original line number Diff line number Diff line 
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller



The BCM2835 contains a custom top-level interrupt controller, which supports

72 interrupt sources using a 2-level register scheme. The interrupt

controller, or the HW block containing it, is referred to occasionally

as "armctrl" in the SoC documentation, hence naming of this binding.



Required properties:



- compatible : should be "brcm,bcm2835-armctrl-ic.txt"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 2.



  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic

  pending" register, or 1/2 respectively for interrupts in the "IRQ pending

  1/2" register.



  The 2nd cell contains the interrupt number within the bank. Valid values

  are 0..7 for bank 0, and 0..31 for bank 1.



The interrupt sources are as follows:



Bank 0:

0: ARM_TIMER

1: ARM_MAILBOX

2: ARM_DOORBELL_0

3: ARM_DOORBELL_1

4: VPU0_HALTED

5: VPU1_HALTED

6: ILLEGAL_TYPE0

7: ILLEGAL_TYPE1



Bank 1:

0: TIMER0

1: TIMER1

2: TIMER2

3: TIMER3

4: CODEC0

5: CODEC1

6: CODEC2

7: VC_JPEG

8: ISP

9: VC_USB

10: VC_3D

11: TRANSPOSER

12: MULTICORESYNC0

13: MULTICORESYNC1

14: MULTICORESYNC2

15: MULTICORESYNC3

16: DMA0

17: DMA1

18: VC_DMA2

19: VC_DMA3

20: DMA4

21: DMA5

22: DMA6

23: DMA7

24: DMA8

25: DMA9

26: DMA10

27: DMA11

28: DMA12

29: AUX

30: ARM

31: VPUDMA



Bank 2:

0: HOSTPORT

1: VIDEOSCALER

2: CCP2TX

3: SDC

4: DSI0

5: AVE

6: CAM0

7: CAM1

8: HDMI0

9: HDMI1

10: PIXELVALVE1

11: I2CSPISLV

12: DSI1

13: PWA0

14: PWA1

15: CPR

16: SMI

17: GPIO0

18: GPIO1

19: GPIO2

20: GPIO3

21: VC_I2C

22: VC_SPI

23: VC_I2SPCM

24: VC_SDIO

25: VC_UART

26: SLIMBUS

27: VEC

28: CPG

29: RNG

30: VC_ARASANSDIO

31: AVSPMON



Example:



intc: interrupt-controller {

	compatible = "brcm,bcm2835-armctrl-ic";

	reg = <0x7e00b200 0x200>;

	interrupt-controller;

	#interrupt-cells = <2>;

};

Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
BCM2835 System Timer



The System Timer peripheral provides four 32-bit timer channels and a

single 64-bit free running counter. Each channel has an output compare

register, which is compared against the 32 least significant bits of the

free running counter values, and generates an interrupt.



Required properties:



- compatible : should be "brcm,bcm2835-system-timer.txt"

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 4 interrupt sinks; one per timer channel.

- clock-frequency : The frequency of the clock that drives the counter, in Hz.



Example:



timer {

	compatible = "brcm,bcm2835-system-timer";

	reg = <0x7e003000 0x1000>;

	interrupts = <1 0>, <1 1>, <1 2>, <1 3>;

	clock-frequency = <1000000>;

};

Documentation/devicetree/bindings/vendor-prefixes.txt

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ apm Applied Micro Circuits Corporation (APM) 
arm	ARM Ltd.

atmel	Atmel Corporation

bosch	Bosch Sensortec GmbH

brcm	Broadcom Corporation

cavium	Cavium, Inc.

chrp	Common Hardware Reference Platform

cortina	Cortina Systems, Inc.

MAINTAINERS

+10 −0
Original line number Diff line number Diff line
@@ -1612,6 +1612,16 @@ L: netdev@vger.kernel.org 
S:	Supported

F:	drivers/net/ethernet/broadcom/bnx2x/



BROADCOM BCM2835 ARM ARCHICTURE

M:	Stephen Warren <swarren@wwwdotorg.org>

L:	linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git

S:	Maintained

F:	arch/arm/mach-bcm2835/

F:	arch/arm/boot/dts/bcm2835*

F:	arch/arm/configs/bcm2835_defconfig

F:	drivers/*/*bcm2835*



BROADCOM TG3 GIGABIT ETHERNET DRIVER

M:	Matt Carlson <mcarlson@broadcom.com>

M:	Michael Chan <mchan@broadcom.com>

CRA Git | Maintained and supported by SUSTech CRA and CCSE