Commit ea832c41 authored by Olof Johansson's avatar Olof Johansson
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Merge branch 'next/dt' into next/multiplatform 

* next/dt: (182 commits)
  ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
  ARM: tegra: Add Avionic Design Medcom-Wide support
  ARM: tegra: Add Avionic Design Plutux support
  ARM: tegra: Add Avionic Design Tamonten support
  ARM: tegra: dts: Add pwm label
  ARM: dt: tegra: whistler: configure power off
  ARM: mxs: m28evk: Disable OCOTP OUI loading
  ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent
  ARM: dts: imx6q-sabrelite: add usbotg pinctrl support
  ARM: dts: imx23-olinuxino: Add USB host support
  ARM: dts: imx6q-sabrelite: add usbmisc device
  ARM: dts: mx23: Add USB resources
  ARM: dts: mxs: Add ethernetX to macX aliases
  ARM: msm: Remove non-DT targets from 8960
  ARM: msm: Add DT support for 8960
  ARM: msm: Move io mapping prototypes to common.h
  ARM: msm: Rename board-msm8x60 to signify its DT only status
  ARM: msm: Make 8660 a DT only target
  ARM: msm: Move 8660 to DT timer
  ARM: msm: Add DT support to msm_timer
  ...
parents b74aae9a 84bae6c3

Documentation/devicetree/bindings/arm/mrvl/tauros2.txt

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* Marvell Tauros2 Cache



Required properties:

- compatible : Should be "marvell,tauros2-cache".

- marvell,tauros2-cache-features : Specify the features supported for the

  tauros2 cache.

  The features including

    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)

    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)

  The definition can be found at

  arch/arm/include/asm/hardware/cache-tauros2.h



Example:

	L2: l2-cache {

		compatible = "marvell,tauros2-cache";

		marvell,tauros2-cache-features = <0x3>;

	};

Documentation/devicetree/bindings/arm/msm/timer.txt

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* MSM Timer



Properties:



- compatible : Should at least contain "qcom,msm-timer". More specific

  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general

  purpose timer and a debug timer respectively.



- interrupts : Interrupt indicating a match event.



- reg : Specifies the base address of the timer registers. The second region

  specifies an optional register used to configure the clock divider.



- clock-frequency : The frequency of the timer in Hz.



Optional:



- cpu-offset : per-cpu offset used when the timer is accessed without the

  CPU remapping facilities. The offset is cpu-offset * cpu-nr.



Example:



       timer@200a004 {

               compatible = "qcom,msm-gpt", "qcom,msm-timer";

               interrupts = <1 2 0x301>;

               reg = <0x0200a004 0x10>;

               clock-frequency = <32768>;

               cpu-offset = <0x40000>;

       };



       timer@200a024 {

               compatible = "qcom,msm-dgt", "qcom,msm-timer";

               interrupts = <1 3 0x301>;

               reg = <0x0200a024 0x10>,

                     <0x0200a034 0x4>;

               clock-frequency = <6750000>;

               cpu-offset = <0x40000>;

       };

Documentation/devicetree/bindings/arm/omap/omap.txt

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@@ -36,6 +36,9 @@ Boards: 
- OMAP3 BeagleBoard : Low cost community board

  compatible = "ti,omap3-beagle", "ti,omap3"



- OMAP3 Tobi with Overo : Commercial expansion board with daughter board

  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"



- OMAP4 SDP : Software Developement Board

  compatible = "ti,omap4-sdp", "ti,omap4430"

Documentation/devicetree/bindings/clock/imx23-clock.txt

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* Clock bindings for Freescale i.MX23



Required properties:

- compatible: Should be "fsl,imx23-clkctrl"

- reg: Address and length of the register set

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX23

clocks and IDs.



	Clock		ID

	------------------

	ref_xtal	0

	pll		1

	ref_cpu		2

	ref_emi		3

	ref_pix		4

	ref_io		5

	saif_sel	6

	lcdif_sel	7

	gpmi_sel	8

	ssp_sel		9

	emi_sel		10

	cpu		11

	etm_sel		12

	cpu_pll		13

	cpu_xtal	14

	hbus		15

	xbus		16

	lcdif_div	17

	ssp_div		18

	gpmi_div	19

	emi_pll		20

	emi_xtal	21

	etm_div		22

	saif_div	23

	clk32k_div	24

	rtc		25

	adc		26

	spdif_div	27

	clk32k		28

	dri		29

	pwm		30

	filt		31

	uart		32

	ssp		33

	gpmi		34

	spdif		35

	emi		36

	saif		37

	lcdif		38

	etm		39

	usb		40

	usb_pwr		41



Examples:



clks: clkctrl@80040000 {

	compatible = "fsl,imx23-clkctrl";

	reg = <0x80040000 0x2000>;

	#clock-cells = <1>;

	clock-output-names =

		...

		"uart",		/* 32 */

		...

		"end_of_list";

};



auart0: serial@8006c000 {

	compatible = "fsl,imx23-auart";

	reg = <0x8006c000 0x2000>;

	interrupts = <24 25 23>;

	clocks = <&clks 32>;

	status = "disabled";

};

Documentation/devicetree/bindings/clock/imx28-clock.txt

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* Clock bindings for Freescale i.MX28



Required properties:

- compatible: Should be "fsl,imx28-clkctrl"

- reg: Address and length of the register set

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX28

clocks and IDs.



	Clock		ID

	------------------

	ref_xtal	0

	pll0		1

	pll1		2

	pll2		3

	ref_cpu		4

	ref_emi		5

	ref_io0		6

	ref_io1		7

	ref_pix		8

	ref_hsadc	9

	ref_gpmi	10

	saif0_sel	11

	saif1_sel	12

	gpmi_sel	13

	ssp0_sel	14

	ssp1_sel	15

	ssp2_sel	16

	ssp3_sel	17

	emi_sel		18

	etm_sel		19

	lcdif_sel	20

	cpu		21

	ptp_sel		22

	cpu_pll		23

	cpu_xtal	24

	hbus		25

	xbus		26

	ssp0_div	27

	ssp1_div	28

	ssp2_div	29

	ssp3_div	30

	gpmi_div	31

	emi_pll		32

	emi_xtal	33

	lcdif_div	34

	etm_div		35

	ptp		36

	saif0_div	37

	saif1_div	38

	clk32k_div	39

	rtc		40

	lradc		41

	spdif_div	42

	clk32k		43

	pwm		44

	uart		45

	ssp0		46

	ssp1		47

	ssp2		48

	ssp3		49

	gpmi		50

	spdif		51

	emi		52

	saif0		53

	saif1		54

	lcdif		55

	etm		56

	fec		57

	can0		58

	can1		59

	usb0		60

	usb1		61

	usb0_pwr	62

	usb1_pwr	63

	enet_out	64



Examples:



clks: clkctrl@80040000 {

	compatible = "fsl,imx28-clkctrl";

	reg = <0x80040000 0x2000>;

	#clock-cells = <1>;

	clock-output-names =

		...

		"uart",		/* 45 */

		...

		"end_of_list";

};



auart0: serial@8006a000 {

	compatible = "fsl,imx28-auart", "fsl,imx23-auart";

	reg = <0x8006a000 0x2000>;

	interrupts = <112 70 71>;

	clocks = <&clks 45>;

	status = "disabled";

};

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