Commit b5ff7f27 authored by Jin Yao's avatar Jin Yao Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update SkylakeX events to v1.21 



- Update SkylakeX events to v1.21.
- Update SkylakeX JSON metrics from TMAM 4.0.

Other fixes:

- Add NO_NMI_WATCHDOG metric constraint to Backend_Bound
- Fix misspelled error

Signed-off-by: default avatarJin Yao <yao.jin@linux.intel.com>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/lkml/20200922031918.3723-1-yao.jin@linux.intel.com/


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 038d3b53

tools/perf/pmu-events/arch/x86/skylakex/cache.json

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tools/perf/pmu-events/arch/x86/skylakex/floating-point.json

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[

    {

        "EventCode": "0xC7",

        "UMask": "0x1",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x2",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x40"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x4",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x8",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x10"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x10",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x80"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x20",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x20"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x40",

        "BriefDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "SampleAfterValue": "100003",

        "UMask": "0x1e"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x80",

        "BriefDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x1e",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.ANY",

        "CounterMask": "1",

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    }

]
 
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tools/perf/pmu-events/arch/x86/skylakex/frontend.json

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tools/perf/pmu-events/arch/x86/skylakex/memory.json

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tools/perf/pmu-events/arch/x86/skylakex/other.json

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[

    {

        "EventCode": "0x28",

        "UMask": "0x7",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",

        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",

        "SampleAfterValue": "200003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x28",

        "UMask": "0x18",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",

        "EventName": "CORE_POWER.THROTTLE",

        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",

        "SampleAfterValue": "200003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x40"

    },

    {

        "EventCode": "0x28",

        "UMask": "0x20",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",

        "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",

        "Counter": "0,1,2,3",

        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",

        "SampleAfterValue": "200003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xFE",

        "EventName": "IDI_MISC.WB_DOWNGRADE",

        "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",

        "SampleAfterValue": "100003",

        "UMask": "0x4"

    },

    {

        "EventCode": "0x28",

        "UMask": "0x40",

        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",

        "BriefDescription": "Number of PREFETCHW instructions executed.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_POWER.THROTTLE",

        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",

        "SampleAfterValue": "200003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "UMask": "0x1",

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "Counter": "0,1,2,3",

        "EventName": "SW_PREFETCH_ACCESS.NTA",

        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "EventCode": "0x32",

        "UMask": "0x2",

        "BriefDescription": "Number of PREFETCHT0 instructions executed.",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",

        "Counter": "0,1,2,3",

        "EventName": "SW_PREFETCH_ACCESS.T0",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",

        "SampleAfterValue": "200003",

        "UMask": "0x7"

    },

    {

        "EventCode": "0x32",

        "UMask": "0x4",

        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",

        "Counter": "0,1,2,3",

        "EventName": "SW_PREFETCH_ACCESS.T1_T2",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",

        "SampleAfterValue": "200003",

        "UMask": "0x18"

    },

    {

        "EventCode": "0x32",

        "UMask": "0x8",

        "BriefDescription": "Number of PREFETCHW instructions executed.",

        "BriefDescription": "Number of PREFETCHT0 instructions executed.",

        "Counter": "0,1,2,3",

        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.T0",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xCB",

        "UMask": "0x1",

        "BriefDescription": "Number of hardware interrupts received by the processor.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCB",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",

        "SampleAfterValue": "203",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x1",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x2",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x4",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x8",

        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",

        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",

        "SampleAfterValue": "200003",

        "UMask": "0x20"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x10",

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.NTA",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x20",

        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.T1_T2",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "EventCode": "0xEF",

        "UMask": "0x40",

        "Counter": "0,1,2,3",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x09",

        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "EventCode": "0xFE",

        "UMask": "0x2",

        "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xFE",

        "EventName": "IDI_MISC.WB_UPGRADE",

        "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xFE",

        "UMask": "0x4",

        "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",

        "Counter": "0,1,2,3",

        "EventName": "IDI_MISC.WB_DOWNGRADE",

        "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    }

]
 
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