Commit 038d3b53 authored by Jin Yao's avatar Jin Yao Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update CascadelakeX events to v1.08 



- Update CascadelakeX events to v1.08.
- Update CascadelakeX JSON metrics from TMAM 4.0.

Other fixes:

- Add NO_NMI_WATCHDOG metric constraint to Backend_Bound
- Change 'MB/sec' to 'MB' in UNC_M_PMM_BANDWIDTH.

Signed-off-by: default avatarJin Yao <yao.jin@linux.intel.com>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Link: https://lore.kernel.org/lkml/20200922031918.3723-1-yao.jin@linux.intel.com/


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 69f48c70

tools/perf/pmu-events/arch/x86/cascadelakex/cache.json

+14 −14
Original line number Diff line number Diff line
@@ -8063,6 +8063,20 @@ 
        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "Deprecated": "1",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1000020004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",

        "Counter": "0,1,2,3",
@@ -9255,20 +9269,6 @@ 
        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "Deprecated": "1",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1000020004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json

+86 −67

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tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json

+34 −0
Original line number Diff line number Diff line
@@ -246,6 +246,30 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.COUNT",

        "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",

        "SampleAfterValue": "2000003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",

        "Counter": "0,1,2,3,4,5,6,7",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc6",

        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x400106",

        "PEBS": "2",

        "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "TakenAlone": "1",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",

        "Counter": "0,1,2,3",
@@ -359,6 +383,16 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x24"

    },

    {

        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.ANY",

        "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/cascadelakex/memory.json

+356 −348

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tools/perf/pmu-events/arch/x86/cascadelakex/other.json

+550 −550

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