MIPS: Add Cavium OCTEON cop2/cvmseg state entries to processor.h. (b5e00af8) · Commits · 戴 / test

arch/mips/include/asm/processor.h

+69 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,60 @@ union mips_watch_reg_state {
		struct mips3264_watch_reg_state mips3264;
		};

		#ifdef CONFIG_CPU_CAVIUM_OCTEON

		struct octeon_cop2_state {
		/* DMFC2 rt, 0x0201 */
		unsigned long cop2_crc_iv;
		/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
		unsigned long cop2_crc_length;
		/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
		unsigned long cop2_crc_poly;
		/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
		unsigned long cop2_llm_dat[2];
		/* DMFC2 rt, 0x0084 */
		unsigned long cop2_3des_iv;
		/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
		unsigned long cop2_3des_key[3];
		/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
		unsigned long cop2_3des_result;
		/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
		unsigned long cop2_aes_inp0;
		/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
		unsigned long cop2_aes_iv[2];
		/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
		* rt, 0x0107 */
		unsigned long cop2_aes_key[4];
		/* DMFC2 rt, 0x0110 */
		unsigned long cop2_aes_keylen;
		/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
		unsigned long cop2_aes_result[2];
		/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
		* rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
		* 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
		* 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
		* 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
		unsigned long cop2_hsh_datw[15];
		/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
		* rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
		* 0x0256; DMFC2 rt, 0x0257 - Pass2 */
		unsigned long cop2_hsh_ivw[8];
		/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
		unsigned long cop2_gfm_mult[2];
		/* DMFC2 rt, 0x025E - Pass2 */
		unsigned long cop2_gfm_poly;
		/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
		unsigned long cop2_gfm_result[2];
		};
		#define INIT_OCTEON_COP2 {0,}

		struct octeon_cvmseg_state {
		unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
		[cpu_dcache_line_size() / sizeof(unsigned long)];
		};

		#endif

		typedef struct {
		unsigned long seg;
		} mm_segment_t;
		@@ -160,6 +214,10 @@ struct thread_struct {
		unsigned long trap_no;
		unsigned long irix_trampoline; /* Wheee... */
		unsigned long irix_oldctx;
		#ifdef CONFIG_CPU_CAVIUM_OCTEON
		struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
		struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
		#endif
		struct mips_abi *abi;
		};

		@@ -171,6 +229,13 @@ struct thread_struct {
		#define FPAFF_INIT
		#endif /* CONFIG_MIPS_MT_FPAFF */

		#ifdef CONFIG_CPU_CAVIUM_OCTEON
		#define OCTEON_INIT \
		.cp2 = INIT_OCTEON_COP2,
		#else
		#define OCTEON_INIT
		#endif /* CONFIG_CPU_CAVIUM_OCTEON */

		#define INIT_THREAD { \
		/* \
		* Saved main processor registers \
		@@ -221,6 +286,10 @@ struct thread_struct {
		.trap_no = 0, \
		.irix_trampoline = 0, \
		.irix_oldctx = 0, \
		/* \
		* Cavium Octeon specifics (null if not Octeon) \
		*/ \
		OCTEON_INIT \
		}

		struct task_struct;

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