MIPS: Modify core io.h macros to account for the Octeon Errata Core-301. (8faca49a) · Commits · 戴 / test

arch/mips/include/asm/io.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
		#undef __IS_KSEG1
		}

		#ifdef CONFIG_CPU_CAVIUM_OCTEON
		#define war_octeon_io_reorder_wmb() wmb()
		#else
		#define war_octeon_io_reorder_wmb() do { } while (0)
		#endif

		#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
		\
		static inline void pfx##write##bwlq(type val, \
		@@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \
		volatile type *__mem; \
		type __val; \
		\
		war_octeon_io_reorder_wmb(); \
		\
		__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
		\
		__val = pfx##ioswab##bwlq(__mem, val); \
		@@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
		volatile type *__addr; \
		type __val; \
		\
		war_octeon_io_reorder_wmb(); \
		\
		__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
		\
		__val = pfx##ioswab##bwlq(__addr, val); \
		@@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
		#endif


		#ifdef CONFIG_CPU_CAVIUM_OCTEON
		#define mmiowb() wmb()
		#else
		/* Depends on MIPS II instruction set */
		#define mmiowb() asm volatile ("sync" ::: "memory")
		#endif

		static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
		{