Commit b5b4717e authored by Manikanta Maddireddy's avatar Manikanta Maddireddy Committed by Lorenzo Pieralisi
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PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20



Cacheable upstream transactions are supported in Tegra20 and Tegra186
only.

AFI_CACHE_BAR_{0,1}_{ST,SZ} registers are available in Tegra20 to
support cacheable upstream transactions. In Tegra186, AFI_AXCACHE
register is defined instead of AFI_CACHE_BAR_{0,1}_{ST,SZ} to be in line
with its memory subsystem design.

Therefore, program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20.

Signed-off-by: default avatarManikanta Maddireddy <mmaddireddy@nvidia.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
parent eef4a350
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+13 −5
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ struct tegra_pcie_soc {
	bool program_deskew_time;
	bool raw_violation_fixup;
	bool update_fc_timer;
	bool has_cache_bars;
	struct {
		struct {
			u32 rp_ectl_2_r1;
@@ -932,11 +933,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
	afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
	afi_writel(pcie, 0, AFI_FPCI_BAR5);

	if (pcie->soc->has_cache_bars) {
		/* map all upstream transactions as uncached */
		afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
		afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
		afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
		afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
	}

	/* MSI translations are setup only when needed */
	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
@@ -2460,6 +2463,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
	.program_deskew_time = false,
	.raw_violation_fixup = false,
	.update_fc_timer = false,
	.has_cache_bars = true,
	.ectl.enable = false,
};

@@ -2488,6 +2492,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
	.program_deskew_time = false,
	.raw_violation_fixup = false,
	.update_fc_timer = false,
	.has_cache_bars = false,
	.ectl.enable = false,
};

@@ -2511,6 +2516,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
	.program_deskew_time = false,
	.raw_violation_fixup = true,
	.update_fc_timer = false,
	.has_cache_bars = false,
	.ectl.enable = false,
};

@@ -2534,6 +2540,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
	.program_deskew_time = true,
	.raw_violation_fixup = false,
	.update_fc_timer = true,
	.has_cache_bars = false,
	.ectl = {
		.regs = {
			.rp_ectl_2_r1 = 0x0000000f,
@@ -2574,6 +2581,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
	.program_deskew_time = false,
	.raw_violation_fixup = false,
	.update_fc_timer = false,
	.has_cache_bars = false,
	.ectl.enable = false,
};