Commit eef4a350 authored by Manikanta Maddireddy's avatar Manikanta Maddireddy Committed by Lorenzo Pieralisi
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PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal 



Disable controllers which failed to bring the link up and configure
CLKREQ# signals of these controllers as GPIO. This is required to avoid
CLKREQ# signal of inactive controllers interfering with PLLE power down
sequence.

PCIE_CLKREQ_GPIO bits are defined only in Tegra186, however programming
these bits in other SoCs doesn't cause any side effects. Program these
bits for all Tegra SoCs to avoid a conditional check.

Signed-off-by: default avatarManikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
parent c23ae2ae

drivers/pci/controller/pci-tegra.c

+12 −1
Original line number Diff line number Diff line
@@ -160,6 +160,8 @@ 
#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211	(0x1 << 20)

#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411	(0x2 << 20)

#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111	(0x2 << 20)

#define  AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x)		(1 << ((x) + 29))

#define  AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL		(0x7 << 29)



#define AFI_FUSE			0x104

#define  AFI_FUSE_PCIE_T0_GEN2_DIS	(1 << 2)
@@ -741,6 +743,12 @@ static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 


	value &= ~AFI_PEX_CTRL_REFCLK_EN;

	afi_writel(port->pcie, value, ctrl);



	/* disable PCIe port and set CLKREQ# as GPIO to allow PLLE power down */

	value = afi_readl(port->pcie, AFI_PCIE_CONFIG);

	value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);

	value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);

	afi_writel(port->pcie, value, AFI_PCIE_CONFIG);

}



static void tegra_pcie_port_free(struct tegra_pcie_port *port)
@@ -1153,9 +1161,12 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie) 
	value = afi_readl(pcie, AFI_PCIE_CONFIG);

	value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;

	value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;

	value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL;



	list_for_each_entry(port, &pcie->ports, list)

	list_for_each_entry(port, &pcie->ports, list) {

		value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);

		value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);

	}



	afi_writel(pcie, value, AFI_PCIE_CONFIG);

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