Commit b53a1603 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next 

 - Add some trace points for clk_set_rate() "range" functions
 - DVFS support for AT91 clk driver

* clk-ti:
  clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
  clk: ti: Fix memleak in ti_fapll_synth_setup

* clk-analog:
  clk: axi-clkgen: move the OF table at the bottom of the file
  clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
  dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format

* clk-trace:
  clk: Trace clk_set_rate() "range" functions

* clk-at91:
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error

* clk-silabs:
  clk: si5351: Wait for bit clear after PLL reset
parents 699eda28 66cc7af3 16214f97 03813d9b 01324f9e 5142cbce

Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml

0 → 100644
+53 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding for Analog Devices AXI clkgen pcore clock generator



maintainers:

  - Lars-Peter Clausen <lars@metafoo.de>

  - Michael Hennerich <michael.hennerich@analog.com>



description: |

  The axi_clkgen IP core is a software programmable clock generator,

  that can be synthesized on various FPGA platforms.



  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen



properties:

  compatible:

    enum:

      - adi,axi-clkgen-2.00.a



  clocks:

    description:

      Specifies the reference clock(s) from which the output frequency is

      derived. This must either reference one clock if only the first clock

      input is connected or two if both clock inputs are connected.

    minItems: 1

    maxItems: 2



  '#clock-cells':

    const: 0



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@ff000000 {

      compatible = "adi,axi-clkgen-2.00.a";

      #clock-cells = <0>;

      reg = <0xff000000 0x1000>;

      clocks = <&osc 1>;

    };

Documentation/devicetree/bindings/clock/axi-clkgen.txt

deleted100644 → 0
+0 −25
Original line number Diff line number Diff line 
Binding for the axi-clkgen clock generator



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".

- #clock-cells : from common clock binding; Should always be set to 0.

- reg : Address and length of the axi-clkgen register set.

- clocks : Phandle and clock specifier for the parent clock(s). This must

	either reference one clock if only the first clock input is connected or two

	if both clock inputs are connected. For the later case the clock connected

	to the first input must be specified first.



Optional properties:

- clock-output-names : From common clock binding.



Example:

	clock@ff000000 {

		compatible = "adi,axi-clkgen";

		#clock-cells = <0>;

		reg = <0xff000000 0x1000>;

		clocks = <&osc 1>;

	};

drivers/clk/at91/at91rm9200.c

+17 −4
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 


#include "pmc.h"



static DEFINE_SPINLOCK(rm9200_mck_lock);



struct sck {

	char *n;

	char *p;
@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) 
	parent_names[1] = "mainck";

	parent_names[2] = "pllack";

	parent_names[3] = "pllbck";

	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,

	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,

					   parent_names,

					   &at91rm9200_master_layout,

					   &rm9200_mck_characteristics,

					   &rm9200_mck_lock, CLK_SET_RATE_GATE,

					   INT_MIN);

	if (IS_ERR(hw))

		goto err_free;



	hw = at91_clk_register_master_div(regmap, "masterck_div",

					  "masterck_pres",

					  &at91rm9200_master_layout,

				      &rm9200_mck_characteristics);

					  &rm9200_mck_characteristics,

					  &rm9200_mck_lock, CLK_SET_RATE_GATE);

	if (IS_ERR(hw))

		goto err_free;
@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) 
	for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {

		hw = at91_clk_register_peripheral(regmap,

						  at91rm9200_periphck[i].n,

						  "masterck",

						  "masterck_div",

						  at91rm9200_periphck[i].id);

		if (IS_ERR(hw))

			goto err_free;

drivers/clk/at91/at91sam9260.c

+20 −6
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ struct at91sam926x_data { 
	bool has_slck;

};



static DEFINE_SPINLOCK(at91sam9260_mck_lock);



static const struct clk_master_characteristics sam9260_mck_characteristics = {

	.output = { .min = 0, .max = 105000000 },

	.divisors = { 1, 2, 4, 0 },
@@ -218,8 +220,8 @@ static const struct sck at91sam9261_systemck[] = { 
	{ .n = "pck1",  .p = "prog1",    .id = 9 },

	{ .n = "pck2",  .p = "prog2",    .id = 10 },

	{ .n = "pck3",  .p = "prog3",    .id = 11 },

	{ .n = "hclk0", .p = "masterck", .id = 16 },

	{ .n = "hclk1", .p = "masterck", .id = 17 },

	{ .n = "hclk0", .p = "masterck_div", .id = 16 },

	{ .n = "hclk1", .p = "masterck_div", .id = 17 },

};



static const struct pck at91sam9261_periphck[] = {
@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, 
	parent_names[1] = "mainck";

	parent_names[2] = "pllack";

	parent_names[3] = "pllbck";

	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,

	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,

					   parent_names,

					   &at91rm9200_master_layout,

					   data->mck_characteristics,

					   &at91sam9260_mck_lock,

					   CLK_SET_RATE_GATE, INT_MIN);

	if (IS_ERR(hw))

		goto err_free;



	hw = at91_clk_register_master_div(regmap, "masterck_div",

					  "masterck_pres",

					  &at91rm9200_master_layout,

				      data->mck_characteristics);

					  data->mck_characteristics,

					  &at91sam9260_mck_lock,

					  CLK_SET_RATE_GATE);

	if (IS_ERR(hw))

		goto err_free;
@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, 
	for (i = 0; i < data->num_pck; i++) {

		hw = at91_clk_register_peripheral(regmap,

						  data->pck[i].n,

						  "masterck",

						  "masterck_div",

						  data->pck[i].id);

		if (IS_ERR(hw))

			goto err_free;

drivers/clk/at91/at91sam9g45.c

+23 −9
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 


#include "pmc.h"



static DEFINE_SPINLOCK(at91sam9g45_mck_lock);



static const struct clk_master_characteristics mck_characteristics = {

	.output = { .min = 0, .max = 133333333 },

	.divisors = { 1, 2, 4, 3 },
@@ -40,7 +42,7 @@ static const struct { 
	char *p;

	u8 id;

} at91sam9g45_systemck[] = {

	{ .n = "ddrck", .p = "masterck", .id = 2 },

	{ .n = "ddrck", .p = "masterck_div", .id = 2 },

	{ .n = "uhpck", .p = "usbck",        .id = 6 },

	{ .n = "pck0",  .p = "prog0",        .id = 8 },

	{ .n = "pck1",  .p = "prog1",        .id = 9 },
@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) 
	parent_names[1] = "mainck";

	parent_names[2] = "plladivck";

	parent_names[3] = "utmick";

	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,

	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,

					   parent_names,

					   &at91rm9200_master_layout,

					   &mck_characteristics,

					   &at91sam9g45_mck_lock,

					   CLK_SET_RATE_GATE, INT_MIN);

	if (IS_ERR(hw))

		goto err_free;



	hw = at91_clk_register_master_div(regmap, "masterck_div",

					  "masterck_pres",

					  &at91rm9200_master_layout,

				      &mck_characteristics);

					  &mck_characteristics,

					  &at91sam9g45_mck_lock,

					  CLK_SET_RATE_GATE);

	if (IS_ERR(hw))

		goto err_free;
@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) 
	parent_names[1] = "mainck";

	parent_names[2] = "plladivck";

	parent_names[3] = "utmick";

	parent_names[4] = "masterck";

	parent_names[4] = "masterck_div";

	for (i = 0; i < 2; i++) {

		char name[6];
@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) 
	for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {

		hw = at91_clk_register_peripheral(regmap,

						  at91sam9g45_periphck[i].n,

						  "masterck",

						  "masterck_div",

						  at91sam9g45_periphck[i].id);

		if (IS_ERR(hw))

			goto err_free;

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