CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies (b4be0189) · Commits · 戴 / test

MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). So provide support to setup required data to handle Duty cycle by the setting up the minimum frequency for DPLL. 1.4GHz is common for all these devices and is based on Technical Reference Manual information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and equivalent information from DRA75x, DRA72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by:

Nishanth Menon <nm@ti.com> [t-kristo@ti.com: updated for latest dpll init API call] Signed-off-by:

Tero Kristo <t-kristo@ti.com>

Documentation/devicetree/bindings/clock/ti/dpll.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@ Required properties:
		"ti,omap4-dpll-core-clock",
		"ti,omap4-dpll-m4xen-clock",
		"ti,omap4-dpll-j-type-clock",
		"ti,omap5-mpu-dpll-clock",
		"ti,am3-dpll-no-gate-clock",
		"ti,am3-dpll-j-type-clock",
		"ti,am3-dpll-no-gate-j-type-clock",

drivers/clk/ti/dpll.c

+21 −0

Original line number	Diff line number	Diff line
		@@ -433,6 +433,27 @@ static void __init of_ti_omap4_dpll_setup(struct device_node *node)
		CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
		of_ti_omap4_dpll_setup);

		static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
		{
		const struct dpll_data dd = {
		.idlest_mask = 0x1,
		.enable_mask = 0x7,
		.autoidle_mask = 0x7,
		.mult_mask = 0x7ff << 8,
		.div1_mask = 0x7f,
		.max_multiplier = 2047,
		.max_divider = 128,
		.dcc_mask = BIT(22),
		.dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
		.min_divider = 1,
		.modes = (1 << DPLL_LOW_POWER_BYPASS) \| (1 << DPLL_LOCKED),
		};

		of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
		}
		CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
		of_ti_omap5_mpu_dpll_setup);

		static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
		{
		const struct dpll_data dd = {

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