ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) (ce369a54) · Commits · 戴 / test

Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x. MPU DPLL has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). For further information, See the note on OMAP5432 Technical Reference Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5" chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by:

Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by:

Taras Kondratiuk <taras@ti.com> Signed-off-by:

J Keerthy <j-keerthy@ti.com> Signed-off-by:

Nishanth Menon <nm@ti.com> [t-kristo@ti.com: added TRM / DM references for DCC clock rate] Signed-off-by:

Tero Kristo <t-kristo@ti.com>

arch/arm/mach-omap2/dpll3xxx.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -319,6 +319,15 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)

		/* Set DPLL multiplier, divider */
		v = omap2_clk_readl(clk, dd->mult_div1_reg);

		/* Handle Duty Cycle Correction */
		if (dd->dcc_mask) {
		if (dd->last_rounded_rate >= dd->dcc_rate)
		v \|= dd->dcc_mask; /* Enable DCC */
		else
		v &= ~dd->dcc_mask; /* Disable DCC */
		}

		v &= ~(dd->mult_mask \| dd->div1_mask);
		v \|= dd->last_rounded_m << __ffs(dd->mult_mask);
		v \|= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);

include/linux/clk/ti.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,8 @@
		* @idlest_reg: register containing the DPLL idle status bitfield
		* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
		* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
		* @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
		* @dcc_rate: rate atleast which DCC @dcc_mask must be set
		* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
		* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
		* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
		@@ -86,6 +88,8 @@ struct dpll_data {
		u32 idlest_mask;
		u32 dco_mask;
		u32 sddiv_mask;
		u32 dcc_mask;
		unsigned long dcc_rate;
		u32 lpmode_mask;
		u32 m4xen_mask;
		u8 auto_recal_bit;

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