mt76: mt7615: fix control frame rx in monitor mode (b4124a5b) · Commits · 戴 / test

drivers/net/wireless/mediatek/mt76/mt7615/init.c

+12 −1

Original line number	Diff line number	Diff line
		@@ -20,7 +20,7 @@ static void mt7615_phy_init(struct mt7615_dev *dev)

		static void mt7615_mac_init(struct mt7615_dev *dev)
		{
		u32 val;
		u32 val, mask, set;

		/* enable band 0/1 clk */
		mt76_set(dev, MT_CFG_CCR,
		@@ -85,6 +85,17 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
		MT_AGG_ARCR_RATE_DOWN_RATIO_EN \|
		FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) \|
		FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));

		mask = MT_DMA_RCFR0_MCU_RX_MGMT \|
		MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR \|
		MT_DMA_RCFR0_MCU_RX_CTL_BAR \|
		MT_DMA_RCFR0_MCU_RX_BYPASS \|
		MT_DMA_RCFR0_RX_DROPPED_UCAST \|
		MT_DMA_RCFR0_RX_DROPPED_MCAST;
		set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) \|
		FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2);
		mt76_rmw(dev, MT_DMA_BN0RCFR0, mask, set);
		mt76_rmw(dev, MT_DMA_BN1RCFR0, mask, set);
		}

		static int mt7615_init_hardware(struct mt7615_dev *dev)

+10 −0

Original line number	Diff line number	Diff line
		@@ -263,6 +263,11 @@ static void mt7615_configure_filter(struct ieee80211_hw *hw,
		u64 multicast)
		{
		struct mt7615_dev *dev = hw->priv;
		u32 ctl_flags = MT_WF_RFCR1_DROP_ACK \|
		MT_WF_RFCR1_DROP_BF_POLL \|
		MT_WF_RFCR1_DROP_BA \|
		MT_WF_RFCR1_DROP_CFEND \|
		MT_WF_RFCR1_DROP_CFACK;
		u32 flags = 0;

		#define MT76_FILTER(_flag, _hw) do { \
		@@ -296,6 +301,11 @@ static void mt7615_configure_filter(struct ieee80211_hw *hw,

		*total_flags = flags;
		mt76_wr(dev, MT_WF_RFCR, dev->mt76.rxfilter);

		if (*total_flags & FIF_CONTROL)
		mt76_clear(dev, MT_WF_RFCR1, ctl_flags);
		else
		mt76_set(dev, MT_WF_RFCR1, ctl_flags);
		}

		static void mt7615_bss_info_changed(struct ieee80211_hw *hw,

+16 −0

Original line number	Diff line number	Diff line
		@@ -176,6 +176,13 @@
		#define MT_WF_RFCR_DROP_NDPA BIT(20)
		#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)

		#define MT_WF_RFCR1 MT_WF_RMAC(0x004)
		#define MT_WF_RFCR1_DROP_ACK BIT(4)
		#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
		#define MT_WF_RFCR1_DROP_BA BIT(6)
		#define MT_WF_RFCR1_DROP_CFEND BIT(7)
		#define MT_WF_RFCR1_DROP_CFACK BIT(8)

		#define MT_WF_DMA_BASE 0x21800
		#define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))

		@@ -183,6 +190,15 @@
		#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2)
		#define MT_DMA_DCR0_RX_VEC_DROP BIT(17)

		#define MT_DMA_BN0RCFR0 MT_WF_DMA(0x070)
		#define MT_DMA_BN1RCFR0 MT_WF_DMA(0x0b0)
		#define MT_DMA_RCFR0_MCU_RX_MGMT BIT(2)
		#define MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR BIT(3)
		#define MT_DMA_RCFR0_MCU_RX_CTL_BAR BIT(4)
		#define MT_DMA_RCFR0_MCU_RX_BYPASS BIT(21)
		#define MT_DMA_RCFR0_RX_DROPPED_UCAST GENMASK(25, 24)
		#define MT_DMA_RCFR0_RX_DROPPED_MCAST GENMASK(27, 26)

		#define MT_WTBL_BASE 0x30000
		#define MT_WTBL_ENTRY_SIZE 256