Commit b18b396b authored by Brad Volkin's avatar Brad Volkin Committed by Daniel Vetter
Browse files

drm/i915: Reject commands that explicitly generate interrupts 



The driver leaves most interrupts masked during normal operation,
so there would have to be additional work to enable userspace to
safely request/receive an interrupt.

v2: trailing commas, rebased

Signed-off-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f0a346bd

drivers/gpu/drm/i915/i915_cmd_parser.c

+20 −2
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
	      ---------------------------------------------------------- */

static const struct drm_i915_cmd_descriptor common_cmds[] = {

	CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),

	CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      S  ),

	CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),

	CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),

	CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),

	CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
@@ -156,7 +156,7 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = { 
	CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,

	      .bits = {{

			.offset = 1,

			.mask = PIPE_CONTROL_MMIO_WRITE,

			.mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),

			.expected = 0,

	      }},						       ),

};
@@ -186,6 +186,12 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = { 
	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),

	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),

	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),

	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,

	      .bits = {{

			.offset = 0,

			.mask = MI_FLUSH_DW_NOTIFY,

			.expected = 0,

	      }},						       ),

	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),

	/*

	 * MFX_WAIT doesn't fit the way we handle length for most commands.
@@ -199,6 +205,12 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 
	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),

	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),

	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),

	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,

	      .bits = {{

			.offset = 0,

			.mask = MI_FLUSH_DW_NOTIFY,

			.expected = 0,

	      }},						       ),

	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),

};
@@ -206,6 +218,12 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = { 
	CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),

	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  S  ),

	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),

	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,

	      .bits = {{

			.offset = 0,

			.mask = MI_FLUSH_DW_NOTIFY,

			.expected = 0,

	      }},						       ),

	CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),

	CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),

};

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -270,6 +270,7 @@ 
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)

#define   MI_INVALIDATE_TLB		(1<<18)

#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)

#define   MI_FLUSH_DW_NOTIFY		(1<<8)

#define   MI_INVALIDATE_BSD		(1<<7)

#define   MI_FLUSH_DW_USE_GTT		(1<<2)

#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)

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