Commit f0a346bd authored by Brad Volkin's avatar Brad Volkin Committed by Daniel Vetter
Browse files

drm/i915: Enable register whitelist checks 



MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.

MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
unused by userspace components. Leave it rejected.

PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
bits being set. Reject those as well.

v2: trailing commas, rebased

OTC-Tracker: AXIA-4631
Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
Signed-off-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 220375aa

drivers/gpu/drm/i915/i915_cmd_parser.c

+18 −3
Original line number Diff line number Diff line
@@ -122,9 +122,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = { 
	CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),

	CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),

	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),

	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   R  ),

	CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   R  ),

	CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   R  ),

	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,

	      .reg = { .offset = 1, .mask = 0x007FFFFC }               ),

	CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W,

	      .reg = { .offset = 1, .mask = 0x007FFFFC }               ),

	CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W,

	      .reg = { .offset = 1, .mask = 0x007FFFFC }               ),

	CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),

};
@@ -141,9 +144,21 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = { 
	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),

	CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),

	CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),

	CMD(  MEDIA_VFE_STATE,			S3D,   !F,  0xFFFF, B,

	      .bits = {{

			.offset = 2,

			.mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,

			.expected = 0,

	      }},						       ),

	CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),

	CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),

	CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),

	CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,

	      .bits = {{

			.offset = 1,

			.mask = PIPE_CONTROL_MMIO_WRITE,

			.expected = 0,

	      }},						       ),

};



static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ 
#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)

#define   PIPE_CONTROL_CS_STALL				(1<<20)

#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)

#define   PIPE_CONTROL_QW_WRITE				(1<<14)
@@ -371,6 +372,8 @@ 


#define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))

#define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))

#define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))

#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)

#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))

#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))

#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \

CRA Git | Maintained and supported by SUSTech CRA and CCSE