Commit b0be0eff authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-pti-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 pti updates from Thomas Gleixner:
 "The performance deterioration departement provides a few non-scary
  fixes and improvements:

   - Update the cached HLE state when the TSX state is changed via the
     new control register. This ensures feature bit consistency.

   - Exclude the new Zhaoxin CPUs from Spectre V2 and SWAPGS
     vulnerabilities"

* tag 'x86-pti-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/speculation/swapgs: Exclude Zhaoxin CPUs from SWAPGS vulnerability
  x86/speculation/spectre_v2: Exclude Zhaoxin CPUs from SPECTRE_V2
  x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR
parents 3d3b44a6 a84de2fa

arch/x86/kernel/cpu/common.c

+8 −1
Original line number Diff line number Diff line
@@ -1023,6 +1023,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 
#define MSBDS_ONLY		BIT(5)

#define NO_SWAPGS		BIT(6)

#define NO_ITLB_MULTIHIT	BIT(7)

#define NO_SPECTRE_V2		BIT(8)



#define VULNWL(_vendor, _family, _model, _whitelist)	\

	{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
@@ -1084,6 +1085,10 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 
	/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */

	VULNWL_AMD(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),

	VULNWL_HYGON(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),



	/* Zhaoxin Family 7 */

	VULNWL(CENTAUR,	7, X86_MODEL_ANY,	NO_SPECTRE_V2 | NO_SWAPGS),

	VULNWL(ZHAOXIN,	7, X86_MODEL_ANY,	NO_SPECTRE_V2 | NO_SWAPGS),

	{}

};
@@ -1116,6 +1121,8 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
		return;



	setup_force_cpu_bug(X86_BUG_SPECTRE_V1);



	if (!cpu_matches(NO_SPECTRE_V2))

		setup_force_cpu_bug(X86_BUG_SPECTRE_V2);



	if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&

arch/x86/kernel/cpu/tsx.c

+7 −6
Original line number Diff line number Diff line
@@ -115,11 +115,12 @@ void __init tsx_init(void) 
		tsx_disable();



		/*

		 * tsx_disable() will change the state of the

		 * RTM CPUID bit.  Clear it here since it is now

		 * expected to be not set.

		 * tsx_disable() will change the state of the RTM and HLE CPUID

		 * bits. Clear them here since they are now expected to be not

		 * set.

		 */

		setup_clear_cpu_cap(X86_FEATURE_RTM);

		setup_clear_cpu_cap(X86_FEATURE_HLE);

	} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {



		/*
@@ -131,10 +132,10 @@ void __init tsx_init(void) 
		tsx_enable();



		/*

		 * tsx_enable() will change the state of the

		 * RTM CPUID bit.  Force it here since it is now

		 * expected to be set.

		 * tsx_enable() will change the state of the RTM and HLE CPUID

		 * bits. Force them here since they are now expected to be set.

		 */

		setup_force_cpu_cap(X86_FEATURE_RTM);

		setup_force_cpu_cap(X86_FEATURE_HLE);

	}

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE