Commit 3d3b44a6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-core-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The interrupt departement provides:

   - A mechanism to shield isolated tasks from managed interrupts:

     The affinity of managed interrupts is completely controlled by the
     kernel and user space has no influence on them. The reason is that
     the automatically assigned affinity correlates to the multi-queue
     CPU handling of block devices.

     If the generated affinity mask spaws both housekeeping and isolated
     CPUs the interrupt could be routed to an isolated CPU which would
     then be disturbed by I/O submitted by a housekeeping CPU.

     The new mechamism ensures that as long as one housekeeping CPU is
     online in the assigned affinity mask the interrupt is routed to a
     housekeeping CPU.

     If there is no online housekeeping CPU in the affinity mask, then
     the interrupt is routed to an isolated CPU to keep the device queue
     intact, but unless the isolated CPU submits I/O by itself these
     interrupts are not raised.

   - A small addon to the device tree irqdomain core code to avoid
     duplication in irq chip drivers

   - Conversion of the SiFive PLIC to hierarchical domains

   - The usual pile of new irq chip drivers: SiFive GPIO, Aspeed SCI,
     NXP INTMUX, Meson A1 GPIO

   - The first cut of support for the new ARM GICv4.1

   - The usual pile of fixes and improvements in core and driver code"

* tag 'irq-core-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (33 commits)
  genirq, sched/isolation: Isolate from handling managed interrupts
  irqchip/gic-v4.1: Allow direct invalidation of VLPIs
  irqchip/gic-v4.1: Suppress per-VLPI doorbell
  irqchip/gic-v4.1: Add VPE INVALL callback
  irqchip/gic-v4.1: Add VPE eviction callback
  irqchip/gic-v4.1: Add VPE residency callback
  irqchip/gic-v4.1: Add mask/unmask doorbell callbacks
  irqchip/gic-v4.1: Plumb skeletal VPE irqchip
  irqchip/gic-v4.1: Implement the v4.1 flavour of VMOVP
  irqchip/gic-v4.1: Don't use the VPE proxy if RVPEID is set
  irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP
  irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation
  irqchip/gic-v3: Add GICv4.1 VPEID size discovery
  irqchip/gic-v3: Detect GICv4.1 supporting RVPEID
  irqchip/gic-v3-its: Fix get_vlpi_map() breakage with doorbells
  irqdomain: Fix a memory leak in irq_domain_push_irq()
  irqchip: Add NXP INTMUX interrupt multiplexer support
  dt-bindings: interrupt-controller: Add binding for NXP INTMUX interrupt multiplexer
  irqchip: Define EXYNOS_IRQ_COMBINER
  irqchip/meson-gpio: Add support for meson a1 SoCs
  ...
parents ab67f600 43ee7448

Documentation/admin-guide/kernel-parameters.txt

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Original line number Diff line number Diff line
@@ -1934,9 +1934,31 @@ 
			  <cpu number> begins at 0 and the maximum value is

			  "number of CPUs in system - 1".



			The format of <cpu-list> is described above.



			managed_irq



			  Isolate from being targeted by managed interrupts

			  which have an interrupt mask containing isolated

			  CPUs. The affinity of managed interrupts is

			  handled by the kernel and cannot be changed via

			  the /proc/irq/* interfaces.



			  This isolation is best effort and only effective

			  if the automatically assigned interrupt mask of a

			  device queue contains isolated and housekeeping

			  CPUs. If housekeeping CPUs are online then such

			  interrupts are directed to the housekeeping CPU

			  so that IO submitted on the housekeeping CPU

			  cannot disturb the isolated CPU.



			  If a queue's affinity mask contains only isolated

			  CPUs then this parameter has no effect on the

			  interrupt routing decision, though interrupts are

			  only delivered when tasks running on those

			  isolated CPUs submit IO. IO submitted on

			  housekeeping CPUs has no influence on those

			  queues.



			The format of <cpu-list> is described above.



	iucv=		[HW,NET]

Documentation/devicetree/bindings/gpio/sifive,gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SiFive GPIO controller



maintainers:

  - Yash Shah <yash.shah@sifive.com>

  - Paul Walmsley <paul.walmsley@sifive.com>



properties:

  compatible:

    items:

      - const: sifive,fu540-c000-gpio

      - const: sifive,gpio0



  reg:

    maxItems: 1



  interrupts:

    description:

      interrupt mapping one per GPIO. Maximum 16 GPIOs.

    minItems: 1

    maxItems: 16



  interrupt-controller: true



  "#interrupt-cells":

    const: 2



  clocks:

    maxItems: 1



  "#gpio-cells":

    const: 2



  gpio-controller: true



required:

  - compatible

  - reg

  - interrupts

  - interrupt-controller

  - "#interrupt-cells"

  - clocks

  - "#gpio-cells"

  - gpio-controller



additionalProperties: false



examples:

  - |

      #include <dt-bindings/clock/sifive-fu540-prci.h>

      gpio@10060000 {

        compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";

        interrupt-parent = <&plic>;

        interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;

        reg = <0x0 0x10060000 0x0 0x1000>;

        clocks = <&tlclk PRCI_CLK_TLCLK>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

      };



...

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

+1 −0
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@@ -17,6 +17,7 @@ Required properties: 
    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)

    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)

    "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)

    "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt

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Aspeed AST25XX and AST26XX SCU Interrupt Controller



Required Properties:

 - #interrupt-cells		: must be 1

 - compatible			: must be "aspeed,ast2500-scu-ic",

				  "aspeed,ast2600-scu-ic0" or

				  "aspeed,ast2600-scu-ic1"

 - interrupts			: interrupt from the parent controller

 - interrupt-controller		: indicates that the controller receives and

				  fires new interrupts for child busses



Example:



    syscon@1e6e2000 {

        ranges = <0 0x1e6e2000 0x1a8>;



        scu_ic: interrupt-controller@18 {

            #interrupt-cells = <1>;

            compatible = "aspeed,ast2500-scu-ic";

            interrupts = <21>;

            interrupt-controller;

        };

    };

Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale INTMUX interrupt multiplexer



maintainers:

  - Joakim Zhang <qiangqing.zhang@nxp.com>



properties:

  compatible:

    const: fsl,imx-intmux



  reg:

    maxItems: 1



  interrupts:

    minItems: 1

    maxItems: 8

    description: |

      Should contain the parent interrupt lines (up to 8) used to multiplex

      the input interrupts.



  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    description: |

      The 1st cell is hw interrupt number, the 2nd cell is channel index.



  clocks:

    description: ipg clock.



  clock-names:

    const: ipg



required:

  - compatible

  - reg

  - interrupts

  - interrupt-controller

  - '#interrupt-cells'

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    interrupt-controller@37400000 {

        compatible = "fsl,imx-intmux";

        reg = <0x37400000 0x1000>;

        interrupts = <0 16 4>,

                     <0 17 4>,

                     <0 18 4>,

                     <0 19 4>,

                     <0 20 4>,

                     <0 21 4>,

                     <0 22 4>,

                     <0 23 4>;

        interrupt-controller;

        interrupt-parent = <&gic>;

        #interrupt-cells = <2>;

        clocks = <&clk>;

        clock-names = "ipg";

    };

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