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Commit afd1ad62 authored by Martin Blumenstingl's avatar Martin Blumenstingl
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Revert "clk: meson: meson8b: detailed HDMI register HACK" 

This reverts commit f3b9ac1f8bc041f82c7cfeadaf4bc07509a5be5c.
parent 62ca37d8
Pipeline #120 failed with stages
in 11 minutes and 8 seconds
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drivers/clk/meson/clk-pll.c
View file @ afd1ad62
......@@ -408,154 +408,6 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static unsigned long meson_clk_hdmi_pll_m8_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
unsigned int div_mode;
unsigned long rate;
rate = meson_clk_pll_recalc_rate(hw, parent_rate);
div_mode = meson_parm_read(clk->map, &pll->div_mode);
return rate * (div_mode + 1);
}
static long meson_clk_hdmi_pll_m8_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
unsigned long current_rate, best_rate = 0;
unsigned int divider;
for (divider = 1; divider <= BIT(pll->div_mode.width); divider++) {
current_rate = meson_clk_pll_round_rate(hw,
div_u64(rate, divider),
parent_rate) * divider;
printk("%s(%lu, %lu): current rate = %lu, best_rate = %lu\n", __func__, rate, *parent_rate, current_rate, best_rate);
if (!best_rate)
best_rate = current_rate;
else if (abs(rate - current_rate) < abs(rate - best_rate))
best_rate = current_rate;
}
printk("%s: best rate = %lu\n", __func__, best_rate);
return best_rate;
}
static int meson_clk_hdmi_pll_m8_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
bool use_div_mode = false, tdc_cal_en;
unsigned int enabled, m, n, frac, ret;
unsigned long old_rate;
printk("%s(%lu, %lu)\n", __func__, rate, parent_rate);
if (parent_rate == 0 || rate == 0)
return -EINVAL;
old_rate = rate;
ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
if (ret) {
ret = meson_clk_get_pll_settings(div_u64(rate, 2), parent_rate,
&m, &n, pll);
if (ret)
return ret;
use_div_mode = true;
}
printk("%s(%lu, %lu): m: %u, n: %u, use_div_mode: %d\n", __func__, rate, parent_rate, m, n, use_div_mode);
enabled = meson_parm_read(clk->map, &pll->en);
if (enabled)
meson_clk_pll_disable(hw);
meson_parm_write(clk->map, &pll->n, n);
meson_parm_write(clk->map, &pll->m, m);
frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
meson_parm_write(clk->map, &pll->frac, frac);
if (use_div_mode) {
unsigned int reve, filter_acq2;
bool sdm_pr_en, iir_bypass_en;
tdc_cal_en = /* TODO */ false;
if (tdc_cal_en)
reve = 1;
else
reve = 0;
if (true) /* TODO: is this OD_LVDS == 1 */
reve |= BIT(6);
sdm_pr_en = /* TODO */ false;
iir_bypass_en = /* TODO */ false;
if (!sdm_pr_en)
filter_acq2 = 216;
else if (iir_bypass_en)
filter_acq2 = 1882;
else
filter_acq2 = 711;
// TODO: PVT_FIX_EN = 1
meson_parm_write(clk->map, &pll->div_mode, 1);
meson_parm_write(clk->map, &pll->reve, reve);
meson_parm_write(clk->map, &pll->sdm_pr_en, sdm_pr_en ? 1 : 0);
meson_parm_write(clk->map, &pll->lm_w, 6);
meson_parm_write(clk->map, &pll->filter_acq1, 35);
meson_parm_write(clk->map, &pll->filter_acq2, filter_acq2);
meson_parm_write(clk->map, &pll->tdc_en, 0); // exception: 2971
meson_parm_write(clk->map, &pll->iir_bypass_en, iir_bypass_en ? 1 : 0);
} else {
meson_parm_write(clk->map, &pll->div_mode, 0);
meson_parm_write(clk->map, &pll->reve, 0); // exception: m8 1008 and 1080: 64
meson_parm_write(clk->map, &pll->sdm_pr_en, 1);
meson_parm_write(clk->map, &pll->lm_w, 5); // exception: m8 1008 and 1080: 6
meson_parm_write(clk->map, &pll->filter_acq1, 34); // exception: m8 1008 and 1080: 35
meson_parm_write(clk->map, &pll->filter_acq2, 310); // exception: m8 1008 and 1080: 711
meson_parm_write(clk->map, &pll->tdc_en, 2);
meson_parm_write(clk->map, &pll->iir_bypass_en, 1);
tdc_cal_en = true;
}
if (tdc_cal_en) {
meson_parm_write(clk->map, &pll->tdc_cal_en, 1); // exception: m8 1008 and 1080: 0
meson_parm_write(clk->map, &pll->tdc_cal_ig, 2);
meson_parm_write(clk->map, &pll->tdc_cal_off, 5);
meson_parm_write(clk->map, &pll->tdc_off_c, 3);
} else {
meson_parm_write(clk->map, &pll->tdc_cal_en, 0);
meson_parm_write(clk->map, &pll->tdc_cal_ig, 3); // exception: 1296
meson_parm_write(clk->map, &pll->tdc_cal_off, 6);
meson_parm_write(clk->map, &pll->tdc_off_c, 2);
}
/* If the pll is stopped, bail out now */
if (!enabled)
return 0;
if (meson_clk_pll_enable(hw)) {
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
__func__, old_rate);
/*
* FIXME: Do we really need/want this HACK ?
* It looks unsafe. what happens if the clock gets into a
* broken state and we can't lock back on the old_rate ? Looks
* like an infinite recursion is possible
*/
meson_clk_pll_set_rate(hw, old_rate, parent_rate);
}
return 0;
}
/*
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
......@@ -572,17 +424,6 @@ const struct clk_ops meson_clk_pcie_pll_ops = {
};
EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
const struct clk_ops meson_clk_hdmi_pll_m8_ops = {
.init = meson_clk_pll_init,
.recalc_rate = meson_clk_hdmi_pll_m8_recalc_rate,
.round_rate = meson_clk_hdmi_pll_m8_round_rate,
.set_rate = meson_clk_hdmi_pll_m8_set_rate,
.is_enabled = meson_clk_pll_is_enabled,
.enable = meson_clk_pll_enable,
.disable = meson_clk_pll_disable
};
EXPORT_SYMBOL_GPL(meson_clk_hdmi_pll_m8_ops);
const struct clk_ops meson_clk_pll_ops = {
.init = meson_clk_pll_init,
.recalc_rate = meson_clk_pll_recalc_rate,
......
drivers/clk/meson/clk-pll.h
View file @ afd1ad62
......@@ -36,18 +36,6 @@ struct meson_clk_pll_data {
struct parm frac;
struct parm l;
struct parm rst;
struct parm div_mode;
struct parm filter_acq1;
struct parm filter_acq2;
struct parm iir_bypass_en;
struct parm lm_w;
struct parm reve;
struct parm sdm_pr_en;
struct parm tdc_cal_en;
struct parm tdc_cal_ig;
struct parm tdc_cal_off;
struct parm tdc_en;
struct parm tdc_off_c;
const struct reg_sequence *init_regs;
unsigned int init_count;
const struct pll_params_table *table;
......@@ -58,6 +46,5 @@ struct meson_clk_pll_data {
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
extern const struct clk_ops meson_clk_pcie_pll_ops;
extern const struct clk_ops meson_clk_hdmi_pll_m8_ops;
#endif /* __MESON_CLK_PLL_H */
drivers/clk/meson/meson8b.c
View file @ afd1ad62
......@@ -181,66 +181,6 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
.shift = 29,
.width = 1,
},
.div_mode = {
.reg_off = HHI_VID_PLL_CNTL2,
.shift = 14,
.width = 1,
},
.sdm_pr_en = {
.reg_off = HHI_VID_PLL_CNTL2,
.shift = 15,
.width = 1,
},
.lm_w = {
.reg_off = HHI_VID_PLL_CNTL2,
.shift = 28,
.width = 4,
},
.filter_acq1 = {
.reg_off = HHI_VID_PLL_CNTL3,
.shift = 0,
.width = 11,
},
.filter_acq2 = {
.reg_off = HHI_VID_PLL_CNTL3,
.shift = 11,
.width = 11,
},
.tdc_en = {
.reg_off = HHI_VID_PLL_CNTL3,
.shift = 30,
.width = 1,
},
.iir_bypass_en = {
.reg_off = HHI_VID_PLL_CNTL3,
.shift = 31,
.width = 1,
},
.tdc_cal_en = {
.reg_off = HHI_VID_PLL_CNTL4,
.shift = 13,
.width = 1,
},
.tdc_cal_ig = {
.reg_off = HHI_VID_PLL_CNTL4,
.shift = 14,
.width = 2,
},
.reve = {
.reg_off = HHI_VID_PLL_CNTL4,
.shift = 24,
.width = 8,
},
.tdc_cal_off = {
.reg_off = HHI_VID_PLL_CNTL5,
.shift = 0,
.width = 3,
},
.tdc_off_c = {
.reg_off = HHI_VID_PLL_CNTL5,
.shift = 8,
.width = 3,
},
.table = hdmi_pll_params_table,
.init_regs = meson8b_hdmi_pll_init_regs,
.init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
......
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