Commit ae4b4fc1 authored Dec 21, 2010 by Benoit Cousson Committed by Paul Walmsley Dec 21, 2010

OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck

The smartreflex modules belong to an ALWON_FCLK clock domain that
does not have any SW control. The gating of that interface clock
is triggered by a transition of the WKUP clock domain to idle.

Attach both smartreflex instances on OMAP3 to the WKUP clock domain.

The missing clock domain field in srX_fck clock nodes was reported by
Kevin during the discussion about smartreflex on OMAP3:
https://patchwork.kernel.org/patch/199342/



Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>

parent d9b98f5f

arch/arm/mach-omap2/clock3xxx_data.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -3044,6 +3044,7 @@ static struct clk sr1_fck = {
		.parent = &sys_ck,
		.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
		.enable_bit = OMAP3430_EN_SR1_SHIFT,
		.clkdm_name = "wkup_clkdm",
		.recalc = &followparent_recalc,
		};

		@@ -3054,6 +3055,7 @@ static struct clk sr2_fck = {
		.parent = &sys_ck,
		.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
		.enable_bit = OMAP3430_EN_SR2_SHIFT,
		.clkdm_name = "wkup_clkdm",
		.recalc = &followparent_recalc,
		};

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