clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering (ac8cb538) · Commits · 戴 / test

Similar to commit ("clk: rockchip: fix rk3188 sclk_smc gate data") there is one other gate clock in the rk3188 clock driver with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well. Signed-off-by:

Heiko Stuebner <heiko@sntech.de>

drivers/clk/rockchip/clk-rk3188.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
		RK2928_CLKGATE_CON(2), 5, GFLAGS),
		MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
		RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
		GATE(0, "sclk_mac_lbtest", "sclk_macref",
		RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
		GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
		RK2928_CLKGATE_CON(2), 12, GFLAGS),

		COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
		RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,

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