Commit a9f0c0e5 authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

clk: rockchip: fix rk3188 sclk_smc gate data 



Fix sclk_smc gate data.
Change variable order, flags come before the register address.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarJohan Jonker <jbx9999@hotmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 8b19faf6

drivers/clk/rockchip/clk-rk3188.c

+2 −2
Original line number Diff line number Diff line
@@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	 * Clock-Architecture Diagram 4

	 */



	GATE(SCLK_SMC, "sclk_smc", "hclk_peri",

			RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),

	GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,

			RK2928_CLKGATE_CON(2), 4, GFLAGS),



	COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,

			RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,

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