Commit aac7ff20 authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

clk: imx6sll: add mmdc1 ipg clock 



i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 891f30bf

drivers/clk/imx/clk-imx6sll.c

+1 −0
Original line number Diff line number Diff line
@@ -293,6 +293,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SLL_CLK_WDOG1]		= imx_clk_gate2("wdog1",	"ipg",		base + 0x74, 16);

	clks[IMX6SLL_CLK_MMDC_P0_FAST]	= imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf",  base + 0x74,	20, CLK_IS_CRITICAL);

	clks[IMX6SLL_CLK_MMDC_P0_IPG]	= imx_clk_gate2_flags("mmdc_p0_ipg", "ipg",	   base + 0x74,	24, CLK_IS_CRITICAL);

	clks[IMX6SLL_CLK_MMDC_P1_IPG]	= imx_clk_gate2("mmdc_p1_ipg", "ipg",	   base + 0x74,	26);

	clks[IMX6SLL_CLK_OCRAM]		= imx_clk_gate_flags("ocram","ahb",		   base + 0x74,	28, CLK_IS_CRITICAL);



	/* CCGR4 */

include/dt-bindings/clock/imx6sll-clock.h

+2 −1
Original line number Diff line number Diff line
@@ -203,7 +203,8 @@ 
#define IMX6SLL_CLK_GPIO4               176

#define IMX6SLL_CLK_GPIO5               177

#define IMX6SLL_CLK_GPIO6               178

#define IMX6SLL_CLK_MMDC_P1_IPG		179



#define IMX6SLL_CLK_END			179

#define IMX6SLL_CLK_END			180



#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */

CRA Git | Maintained and supported by SUSTech CRA and CCSE