drm/amdgpu: introduce psp_v11_0_is_sos_alive interface(v2) (a7d4c920) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+13 −9

Original line number	Diff line number	Diff line
		@@ -206,18 +206,26 @@ out:
		return err;
		}

		static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
		{
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

		return sol_reg != 0x0;
		}

		static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
		{
		int ret;
		uint32_t psp_gfxdrv_command_reg = 0;
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		/* Check tOS sign of life register to confirm sys driver and sOS
		* are already been loaded.
		*/
		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
		if (sol_reg) {
		if (psp_v11_0_is_sos_alive(psp)) {
		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
		dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
		return 0;
		@@ -253,13 +261,11 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
		int ret;
		uint32_t psp_gfxdrv_command_reg = 0;
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		/* Check sOS sign of life register to confirm sys driver and sOS
		* are already been loaded.
		*/
		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
		if (sol_reg) {
		if (psp_v11_0_is_sos_alive(psp)) {
		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
		dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
		return 0;
		@@ -297,13 +303,11 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
		int ret;
		unsigned int psp_gfxdrv_command_reg = 0;
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		/* Check sOS sign of life register to confirm sys driver and sOS
		* are already been loaded.
		*/
		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
		if (sol_reg)
		if (psp_v11_0_is_sos_alive(psp))
		return 0;

		/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */

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