drm/amdgpu: add a generic fb accessing helper function(v3) (e35e2b11) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -981,6 +981,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
		void amdgpu_device_fini(struct amdgpu_device *adev);
		int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);

		void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
		uint32_t *buf, size_t size, bool write);
		uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
		uint32_t acc_flags);
		void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

+30 −0

Original line number	Diff line number	Diff line
		@@ -153,6 +153,36 @@ bool amdgpu_device_is_px(struct drm_device *dev)
		return false;
		}

		/**
		* VRAM access helper functions.
		*
		* amdgpu_device_vram_access - read/write a buffer in vram
		*
		* @adev: amdgpu_device pointer
		* @pos: offset of the buffer in vram
		* @buf: virtual address of the buffer in system memory
		* @size: read/write size, sizeof(@buf) must > @size
		* @write: true - write to vram, otherwise - read from vram
		*/
		void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
		uint32_t *buf, size_t size, bool write)
		{
		uint64_t last;
		unsigned long flags;

		last = size - 4;
		for (last += pos; pos <= last; pos += 4) {
		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) \| 0x80000000);
		WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
		if (write)
		WREG32_NO_KIQ(mmMM_DATA, *buf++);
		else
		*buf++ = RREG32_NO_KIQ(mmMM_DATA);
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
		}
		}

		/*
		* MMIO register access helper functions.
		*/

+1 −11

Original line number	Diff line number	Diff line
		@@ -134,20 +134,10 @@ static int hw_id_map[MAX_HWIP] = {

		static int amdgpu_discovery_read_binary(struct amdgpu_device adev, uint8_t binary)
		{
		uint32_t p = (uint32_t )binary;
		uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
		uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
		unsigned long flags;

		while (pos < vram_size) {
		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) \| 0x80000000);
		WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
		*p++ = RREG32_NO_KIQ(mmMM_DATA);
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
		pos += 4;
		}

		amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false);
		return 0;
		}