Commit a706d850 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes 

From Shawn Guo, imx fixes for 3.10:

- A few imx6 clock fixes.  Nothing is extremely important, but since
  we're still in early -rc, I send them for 3.10 inclusion.
- Having bootloader handle ARM errata, we will need to replicate the
  diagnostic register of boot cpu into secondary cores, since
  bootloader only sets up boot cpu.  Otherwise, errata workaround simply
  does not work.

* tag 'imx-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6

:
  ARM: imx: fix typo in gpu3d_shader_sels
  ARM: imx: replicate the diagnostic register of boot cpu into secondary cores
  ARM i.MX6: correct MLB clock configuration
  ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7a7e3472 de78a23d

arch/arm/mach-imx/clk-imx6q.c

+6 −5
Original line number Diff line number Diff line
@@ -177,7 +177,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 
static const char *step_sels[]	= { "osc", "pll2_pfd2_396m", };

static const char *pll1_sw_sels[]	= { "pll1_sys", "step", };

static const char *periph_pre_sels[]	= { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };

static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", };

static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy", };

static const char *periph2_clk2_sels[]	= { "pll3_usb_otg", "pll2_bus", };

static const char *periph_sels[]	= { "periph_pre", "periph_clk2", };

static const char *periph2_sels[]	= { "periph2_pre", "periph2_clk2", };

static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
@@ -185,7 +186,7 @@ static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd 
static const char *gpu_axi_sels[]	= { "axi", "ahb", };

static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };

static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };

static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };

static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };

static const char *ipu_sels[]		= { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };

static const char *ldb_di_sels[]	= { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };

static const char *ipu_di_pre_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
@@ -369,8 +370,8 @@ int __init mx6q_clocks_init(void) 
	clk[pll1_sw]          = imx_clk_mux("pll1_sw",	        base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));

	clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));

	clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));

	clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));

	clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));

	clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));

	clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));

	clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));

	clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));

	clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
@@ -498,7 +499,7 @@ int __init mx6q_clocks_init(void) 
	clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);

	clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);

	clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);

	clk[mlb]          = imx_clk_gate2("mlb",           "pll8_mlb",          base + 0x74, 18);

	clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);

	clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);

	clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);

	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);

arch/arm/mach-imx/headsmp.S

+12 −0
Original line number Diff line number Diff line
@@ -18,8 +18,20 @@ 
	.section ".text.head", "ax"



#ifdef CONFIG_SMP

diag_reg_offset:

	.word	g_diag_reg - .



	.macro	set_diag_reg

	adr	r0, diag_reg_offset

	ldr	r1, [r0]

	add	r1, r1, r0		@ r1 = physical &g_diag_reg

	ldr	r0, [r1]

	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

	.endm



ENTRY(v7_secondary_startup)

	bl	v7_invalidate_l1

	set_diag_reg

	b	secondary_startup

ENDPROC(v7_secondary_startup)

#endif

arch/arm/mach-imx/platsmp.c

+14 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include <linux/init.h>

#include <linux/smp.h>

#include <asm/cacheflush.h>

#include <asm/page.h>

#include <asm/smp_scu.h>

#include <asm/mach/map.h>
@@ -21,6 +22,7 @@ 


#define SCU_STANDBY_ENABLE	(1 << 5)



u32 g_diag_reg;

static void __iomem *scu_base;



static struct map_desc scu_io_desc __initdata = {
@@ -80,6 +82,18 @@ void imx_smp_prepare(void) 
static void __init imx_smp_prepare_cpus(unsigned int max_cpus)

{

	imx_smp_prepare();



	/*

	 * The diagnostic register holds the errata bits.  Mostly bootloader

	 * does not bring up secondary cores, so that when errata bits are set

	 * in bootloader, they are set only for boot cpu.  But on a SMP

	 * configuration, it should be equally done on every single core.

	 * Read the register from boot cpu here, and will replicate it into

	 * secondary cores when booting them.

	 */

	asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");

	__cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));

	outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));

}



struct smp_operations  imx_smp_ops __initdata = {

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