Commit a61e365d authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and target 



As a preparation step for the offloading to IS1, let's create the
infrastructure for talking with this hardware block.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c1c3993e

arch/mips/boot/dts/mscc/ocelot.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -134,11 +134,12 @@ 
			      <0x1280000 0x100>,

			      <0x1800000 0x80000>,

			      <0x1880000 0x10000>,

			      <0x1050000 0x10000>,

			      <0x1060000 0x10000>;

			reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",

				    "port2", "port3", "port4", "port5", "port6",

				    "port7", "port8", "port9", "port10", "qsys",

				    "ana", "s2";

				    "ana", "s1", "s2";

			interrupts = <18 21 22>;

			interrupt-names = "ptp_rdy", "xtr", "inj";

drivers/net/dsa/ocelot/felix_vsc9959.c

+92 −0
Original line number Diff line number Diff line
@@ -361,6 +361,7 @@ static const u32 *vsc9959_regmap[TARGET_MAX] = { 
	[QSYS]	= vsc9959_qsys_regmap,

	[REW]	= vsc9959_rew_regmap,

	[SYS]	= vsc9959_sys_regmap,

	[S1]	= vsc9959_vcap_regmap,

	[S2]	= vsc9959_vcap_regmap,

	[PTP]	= vsc9959_ptp_regmap,

	[GCB]	= vsc9959_gcb_regmap,
@@ -394,6 +395,11 @@ static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 
		.end	= 0x001ffff,

		.name	= "sys",

	},

	[S1] = {

		.start	= 0x0050000,

		.end	= 0x00503ff,

		.name	= "s1",

	},

	[S2] = {

		.start	= 0x0060000,

		.end	= 0x00603ff,
@@ -598,6 +604,80 @@ static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 
	{ .offset = 0x111,	.name = "drop_green_prio_7", },

};



static const struct vcap_field vsc9959_vcap_is1_keys[] = {

	[VCAP_IS1_HK_TYPE]			= {  0,   1},

	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},

	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,   7},

	[VCAP_IS1_HK_RSV]			= { 10,   9},

	[VCAP_IS1_HK_OAM_Y1731]			= { 19,   1},

	[VCAP_IS1_HK_L2_MC]			= { 20,   1},

	[VCAP_IS1_HK_L2_BC]			= { 21,   1},

	[VCAP_IS1_HK_IP_MC]			= { 22,   1},

	[VCAP_IS1_HK_VLAN_TAGGED]		= { 23,   1},

	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 24,   1},

	[VCAP_IS1_HK_TPID]			= { 25,   1},

	[VCAP_IS1_HK_VID]			= { 26,  12},

	[VCAP_IS1_HK_DEI]			= { 38,   1},

	[VCAP_IS1_HK_PCP]			= { 39,   3},

	/* Specific Fields for IS1 Half Key S1_NORMAL */

	[VCAP_IS1_HK_L2_SMAC]			= { 42,  48},

	[VCAP_IS1_HK_ETYPE_LEN]			= { 90,   1},

	[VCAP_IS1_HK_ETYPE]			= { 91,  16},

	[VCAP_IS1_HK_IP_SNAP]			= {107,   1},

	[VCAP_IS1_HK_IP4]			= {108,   1},

	/* Layer-3 Information */

	[VCAP_IS1_HK_L3_FRAGMENT]		= {109,   1},

	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {110,   1},

	[VCAP_IS1_HK_L3_OPTIONS]		= {111,   1},

	[VCAP_IS1_HK_L3_DSCP]			= {112,   6},

	[VCAP_IS1_HK_L3_IP4_SIP]		= {118,  32},

	/* Layer-4 Information */

	[VCAP_IS1_HK_TCP_UDP]			= {150,   1},

	[VCAP_IS1_HK_TCP]			= {151,   1},

	[VCAP_IS1_HK_L4_SPORT]			= {152,  16},

	[VCAP_IS1_HK_L4_RNG]			= {168,   8},

	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */

	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},

	[VCAP_IS1_HK_IP4_INNER_VID]		= { 43,  12},

	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 55,   1},

	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 56,   3},

	[VCAP_IS1_HK_IP4_IP4]			= { 59,   1},

	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 60,   1},

	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 61,   1},

	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 62,   1},

	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 63,   6},

	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 69,  32},

	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {101,  32},

	[VCAP_IS1_HK_IP4_L3_PROTO]		= {133,   8},

	[VCAP_IS1_HK_IP4_TCP_UDP]		= {141,   1},

	[VCAP_IS1_HK_IP4_TCP]			= {142,   1},

	[VCAP_IS1_HK_IP4_L4_RNG]		= {143,   8},

	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {151,  32},

};



static const struct vcap_field vsc9959_vcap_is1_actions[] = {

	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},

	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},

	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},

	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},

	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},

	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},

	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},

	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},

	[VCAP_IS1_ACT_RSV]			= { 29,  9},

	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 38,  1},

	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 39, 12},

	[VCAP_IS1_ACT_FID_SEL]			= { 51,  2},

	[VCAP_IS1_ACT_FID_VAL]			= { 53, 13},

	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 66,  1},

	[VCAP_IS1_ACT_PCP_VAL]			= { 67,  3},

	[VCAP_IS1_ACT_DEI_VAL]			= { 70,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 71,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 72,  2},

	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 74,  4},

	[VCAP_IS1_ACT_HIT_STICKY]		= { 78,  1},

};



static struct vcap_field vsc9959_vcap_is2_keys[] = {

	/* Common: 41 bits */

	[VCAP_IS2_TYPE]				= {  0,   4},
@@ -697,6 +777,18 @@ static struct vcap_field vsc9959_vcap_is2_actions[] = { 
};



static const struct vcap_props vsc9959_vcap_props[] = {

	[VCAP_IS1] = {

		.action_type_width = 0,

		.action_table = {

			[IS1_ACTION_TYPE_NORMAL] = {

				.width = 78, /* HIT_STICKY not included */

				.count = 4,

			},

		},

		.target = S1,

		.keys = vsc9959_vcap_is1_keys,

		.actions = vsc9959_vcap_is1_actions,

	},

	[VCAP_IS2] = {

		.tg_width = 2,

		.sw_count = 4,

drivers/net/dsa/ocelot/seville_vsc9953.c

+92 −0
Original line number Diff line number Diff line
@@ -354,6 +354,7 @@ static const u32 *vsc9953_regmap[TARGET_MAX] = { 
	[QSYS]		= vsc9953_qsys_regmap,

	[REW]		= vsc9953_rew_regmap,

	[SYS]		= vsc9953_sys_regmap,

	[S1]		= vsc9953_vcap_regmap,

	[S2]		= vsc9953_vcap_regmap,

	[GCB]		= vsc9953_gcb_regmap,

	[DEV_GMII]	= vsc9953_dev_gmii_regmap,
@@ -386,6 +387,11 @@ static const struct resource vsc9953_target_io_res[TARGET_MAX] = { 
		.end	= 0x001ffff,

		.name	= "sys",

	},

	[S1] = {

		.start	= 0x0050000,

		.end	= 0x00503ff,

		.name	= "s1",

	},

	[S2] = {

		.start	= 0x0060000,

		.end	= 0x00603ff,
@@ -601,6 +607,80 @@ static const struct ocelot_stat_layout vsc9953_stats_layout[] = { 
	{ .offset = 0x91,	.name = "drop_green_prio_7", },

};



static const struct vcap_field vsc9953_vcap_is1_keys[] = {

	[VCAP_IS1_HK_TYPE]			= {  0,   1},

	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},

	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,  11},

	[VCAP_IS1_HK_RSV]			= { 14,  10},

	/* VCAP_IS1_HK_OAM_Y1731 not supported */

	[VCAP_IS1_HK_L2_MC]			= { 24,   1},

	[VCAP_IS1_HK_L2_BC]			= { 25,   1},

	[VCAP_IS1_HK_IP_MC]			= { 26,   1},

	[VCAP_IS1_HK_VLAN_TAGGED]		= { 27,   1},

	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 28,   1},

	[VCAP_IS1_HK_TPID]			= { 29,   1},

	[VCAP_IS1_HK_VID]			= { 30,  12},

	[VCAP_IS1_HK_DEI]			= { 42,   1},

	[VCAP_IS1_HK_PCP]			= { 43,   3},

	/* Specific Fields for IS1 Half Key S1_NORMAL */

	[VCAP_IS1_HK_L2_SMAC]			= { 46,  48},

	[VCAP_IS1_HK_ETYPE_LEN]			= { 94,   1},

	[VCAP_IS1_HK_ETYPE]			= { 95,  16},

	[VCAP_IS1_HK_IP_SNAP]			= {111,   1},

	[VCAP_IS1_HK_IP4]			= {112,   1},

	/* Layer-3 Information */

	[VCAP_IS1_HK_L3_FRAGMENT]		= {113,   1},

	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {114,   1},

	[VCAP_IS1_HK_L3_OPTIONS]		= {115,   1},

	[VCAP_IS1_HK_L3_DSCP]			= {116,   6},

	[VCAP_IS1_HK_L3_IP4_SIP]		= {122,  32},

	/* Layer-4 Information */

	[VCAP_IS1_HK_TCP_UDP]			= {154,   1},

	[VCAP_IS1_HK_TCP]			= {155,   1},

	[VCAP_IS1_HK_L4_SPORT]			= {156,  16},

	[VCAP_IS1_HK_L4_RNG]			= {172,   8},

	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */

	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 46,   1},

	[VCAP_IS1_HK_IP4_INNER_VID]		= { 47,  12},

	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 59,   1},

	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 60,   3},

	[VCAP_IS1_HK_IP4_IP4]			= { 63,   1},

	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 64,   1},

	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 65,   1},

	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 66,   1},

	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 67,   6},

	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 73,  32},

	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {105,  32},

	[VCAP_IS1_HK_IP4_L3_PROTO]		= {137,   8},

	[VCAP_IS1_HK_IP4_TCP_UDP]		= {145,   1},

	[VCAP_IS1_HK_IP4_TCP]			= {146,   1},

	[VCAP_IS1_HK_IP4_L4_RNG]		= {147,   8},

	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {155,  32},

};



static const struct vcap_field vsc9953_vcap_is1_actions[] = {

	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},

	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},

	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},

	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},

	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},

	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},

	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},

	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},

	[VCAP_IS1_ACT_RSV]			= { 29, 11},

	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 40,  1},

	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 41, 12},

	[VCAP_IS1_ACT_FID_SEL]			= { 53,  2},

	[VCAP_IS1_ACT_FID_VAL]			= { 55, 13},

	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 68,  1},

	[VCAP_IS1_ACT_PCP_VAL]			= { 69,  3},

	[VCAP_IS1_ACT_DEI_VAL]			= { 72,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 73,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 74,  2},

	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 76,  4},

	[VCAP_IS1_ACT_HIT_STICKY]		= { 80,  1},

};



static struct vcap_field vsc9953_vcap_is2_keys[] = {

	/* Common: 41 bits */

	[VCAP_IS2_TYPE]				= {  0,   4},
@@ -687,6 +767,18 @@ static struct vcap_field vsc9953_vcap_is2_actions[] = { 
};



static const struct vcap_props vsc9953_vcap_props[] = {

	[VCAP_IS1] = {

		.action_type_width = 0,

		.action_table = {

			[IS1_ACTION_TYPE_NORMAL] = {

				.width = 80, /* HIT_STICKY not included */

				.count = 4,

			},

		},

		.target = S1,

		.keys = vsc9953_vcap_is1_keys,

		.actions = vsc9953_vcap_is1_actions,

	},

	[VCAP_IS2] = {

		.tg_width = 2,

		.sw_count = 4,

drivers/net/ethernet/mscc/ocelot_vsc7514.c

+88 −0
Original line number Diff line number Diff line
@@ -758,6 +758,81 @@ static const struct ocelot_ops ocelot_ops = { 
	.wm_enc			= ocelot_wm_enc,

};



static const struct vcap_field vsc7514_vcap_is1_keys[] = {

	[VCAP_IS1_HK_TYPE]			= {  0,   1},

	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},

	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,  12},

	[VCAP_IS1_HK_RSV]			= { 15,   9},

	[VCAP_IS1_HK_OAM_Y1731]			= { 24,   1},

	[VCAP_IS1_HK_L2_MC]			= { 25,   1},

	[VCAP_IS1_HK_L2_BC]			= { 26,   1},

	[VCAP_IS1_HK_IP_MC]			= { 27,   1},

	[VCAP_IS1_HK_VLAN_TAGGED]		= { 28,   1},

	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 29,   1},

	[VCAP_IS1_HK_TPID]			= { 30,   1},

	[VCAP_IS1_HK_VID]			= { 31,  12},

	[VCAP_IS1_HK_DEI]			= { 43,   1},

	[VCAP_IS1_HK_PCP]			= { 44,   3},

	/* Specific Fields for IS1 Half Key S1_NORMAL */

	[VCAP_IS1_HK_L2_SMAC]			= { 47,  48},

	[VCAP_IS1_HK_ETYPE_LEN]			= { 95,   1},

	[VCAP_IS1_HK_ETYPE]			= { 96,  16},

	[VCAP_IS1_HK_IP_SNAP]			= {112,   1},

	[VCAP_IS1_HK_IP4]			= {113,   1},

	/* Layer-3 Information */

	[VCAP_IS1_HK_L3_FRAGMENT]		= {114,   1},

	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {115,   1},

	[VCAP_IS1_HK_L3_OPTIONS]		= {116,   1},

	[VCAP_IS1_HK_L3_DSCP]			= {117,   6},

	[VCAP_IS1_HK_L3_IP4_SIP]		= {123,  32},

	/* Layer-4 Information */

	[VCAP_IS1_HK_TCP_UDP]			= {155,   1},

	[VCAP_IS1_HK_TCP]			= {156,   1},

	[VCAP_IS1_HK_L4_SPORT]			= {157,  16},

	[VCAP_IS1_HK_L4_RNG]			= {173,   8},

	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */

	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 47,   1},

	[VCAP_IS1_HK_IP4_INNER_VID]		= { 48,  12},

	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 60,   1},

	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 61,   3},

	[VCAP_IS1_HK_IP4_IP4]			= { 64,   1},

	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 65,   1},

	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 66,   1},

	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 67,   1},

	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 68,   6},

	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 74,  32},

	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {106,  32},

	[VCAP_IS1_HK_IP4_L3_PROTO]		= {138,   8},

	[VCAP_IS1_HK_IP4_TCP_UDP]		= {146,   1},

	[VCAP_IS1_HK_IP4_TCP]			= {147,   1},

	[VCAP_IS1_HK_IP4_L4_RNG]		= {148,   8},

	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {156,  32},

};



static const struct vcap_field vsc7514_vcap_is1_actions[] = {

	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},

	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},

	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},

	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},

	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},

	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},

	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},

	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},

	[VCAP_IS1_ACT_RSV]			= { 29,  9},

	/* The fields below are incorrectly shifted by 2 in the manual */

	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 38,  1},

	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 39, 12},

	[VCAP_IS1_ACT_FID_SEL]			= { 51,  2},

	[VCAP_IS1_ACT_FID_VAL]			= { 53, 13},

	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 66,  1},

	[VCAP_IS1_ACT_PCP_VAL]			= { 67,  3},

	[VCAP_IS1_ACT_DEI_VAL]			= { 70,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 71,  1},

	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 72,  2},

	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 74,  4},

	[VCAP_IS1_ACT_HIT_STICKY]		= { 78,  1},

};



static const struct vcap_field vsc7514_vcap_is2_keys[] = {

	/* Common: 46 bits */

	[VCAP_IS2_TYPE]				= {  0,   4},
@@ -857,6 +932,18 @@ static const struct vcap_field vsc7514_vcap_is2_actions[] = { 
};



static const struct vcap_props vsc7514_vcap_props[] = {

	[VCAP_IS1] = {

		.action_type_width = 0,

		.action_table = {

			[IS1_ACTION_TYPE_NORMAL] = {

				.width = 78, /* HIT_STICKY not included */

				.count = 4,

			},

		},

		.target = S1,

		.keys = vsc7514_vcap_is1_keys,

		.actions = vsc7514_vcap_is1_actions,

	},

	[VCAP_IS2] = {

		.tg_width = 2,

		.sw_count = 4,
@@ -1042,6 +1129,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev) 
		{ QSYS, "qsys" },

		{ ANA, "ana" },

		{ QS, "qs" },

		{ S1, "s1" },

		{ S2, "s2" },

		{ PTP, "ptp", 1 },

	};

include/soc/mscc/ocelot.h

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ enum ocelot_target { 
	QSYS,

	REW,

	SYS,

	S1,

	S2,

	HSIO,

	PTP,

CRA Git | Maintained and supported by SUSTech CRA and CCSE