Commit c1c3993e authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: mscc: ocelot: generalize existing code for VCAP 



In the Ocelot switches there are 3 TCAMs: VCAP ES0, IS1 and IS2, which
have the same configuration interface, but different sets of keys and
actions. The driver currently only supports VCAP IS2.

In preparation of VCAP IS1 and ES0 support, the existing code must be
generalized to work with any VCAP.

In that direction, we should move the structures that depend upon VCAP
instantiation, like vcap_is2_keys and vcap_is2_actions, out of struct
ocelot and into struct vcap_props .keys and .actions, a structure that
is replicated 3 times, once per VCAP. We'll pass that structure as an
argument to each function that does the key and action packing - only
the control logic needs to distinguish between ocelot->vcap[VCAP_IS2]
or IS1 or ES0.

Another change is to make use of the newly introduced ocelot_target_read
and ocelot_target_write API, since the 3 VCAPs have the same registers
but put at different addresses.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ed5672d8

drivers/net/dsa/ocelot/felix.c

+0 −2
Original line number Diff line number Diff line
@@ -435,8 +435,6 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) 
	ocelot->num_stats	= felix->info->num_stats;

	ocelot->shared_queue_sz	= felix->info->shared_queue_sz;

	ocelot->num_mact_rows	= felix->info->num_mact_rows;

	ocelot->vcap_is2_keys	= felix->info->vcap_is2_keys;

	ocelot->vcap_is2_actions= felix->info->vcap_is2_actions;

	ocelot->vcap		= felix->info->vcap;

	ocelot->ops		= felix->info->ops;

	ocelot->inj_prefix	= OCELOT_TAG_PREFIX_SHORT;

drivers/net/dsa/ocelot/felix.h

+0 −2
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ struct felix_info { 
	unsigned int			num_stats;

	int				num_ports;

	int				num_tx_queues;

	struct vcap_field		*vcap_is2_keys;

	struct vcap_field		*vcap_is2_actions;

	const struct vcap_props		*vcap;

	int				switch_pci_bar;

	int				imdio_pci_bar;

drivers/net/dsa/ocelot/felix_vsc9959.c

+14 −11
Original line number Diff line number Diff line
@@ -138,14 +138,16 @@ static const u32 vsc9959_qs_regmap[] = { 
	REG_RESERVED(QS_INH_DBG),

};



static const u32 vsc9959_s2_regmap[] = {

	REG(S2_CORE_UPDATE_CTRL,		0x000000),

	REG(S2_CORE_MV_CFG,			0x000004),

	REG(S2_CACHE_ENTRY_DAT,			0x000008),

	REG(S2_CACHE_MASK_DAT,			0x000108),

	REG(S2_CACHE_ACTION_DAT,		0x000208),

	REG(S2_CACHE_CNT_DAT,			0x000308),

	REG(S2_CACHE_TG_DAT,			0x000388),

static const u32 vsc9959_vcap_regmap[] = {

	/* VCAP_CORE_CFG */

	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),

	REG(VCAP_CORE_MV_CFG,			0x000004),

	/* VCAP_CORE_CACHE */

	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),

	REG(VCAP_CACHE_MASK_DAT,		0x000108),

	REG(VCAP_CACHE_ACTION_DAT,		0x000208),

	REG(VCAP_CACHE_CNT_DAT,			0x000308),

	REG(VCAP_CACHE_TG_DAT,			0x000388),

};



static const u32 vsc9959_qsys_regmap[] = {
@@ -359,7 +361,7 @@ static const u32 *vsc9959_regmap[TARGET_MAX] = { 
	[QSYS]	= vsc9959_qsys_regmap,

	[REW]	= vsc9959_rew_regmap,

	[SYS]	= vsc9959_sys_regmap,

	[S2]	= vsc9959_s2_regmap,

	[S2]	= vsc9959_vcap_regmap,

	[PTP]	= vsc9959_ptp_regmap,

	[GCB]	= vsc9959_gcb_regmap,

	[DEV_GMII] = vsc9959_dev_gmii_regmap,
@@ -716,6 +718,9 @@ static const struct vcap_props vsc9959_vcap_props[] = { 
		},

		.counter_words = 4,

		.counter_width = 32,

		.target = S2,

		.keys = vsc9959_vcap_is2_keys,

		.actions = vsc9959_vcap_is2_actions,

	},

};
@@ -1184,8 +1189,6 @@ static const struct felix_info felix_info_vsc9959 = { 
	.ops			= &vsc9959_ops,

	.stats_layout		= vsc9959_stats_layout,

	.num_stats		= ARRAY_SIZE(vsc9959_stats_layout),

	.vcap_is2_keys		= vsc9959_vcap_is2_keys,

	.vcap_is2_actions	= vsc9959_vcap_is2_actions,

	.vcap			= vsc9959_vcap_props,

	.shared_queue_sz	= 128 * 1024,

	.num_mact_rows		= 2048,

drivers/net/dsa/ocelot/seville_vsc9953.c

+14 −11
Original line number Diff line number Diff line
@@ -140,14 +140,16 @@ static const u32 vsc9953_qs_regmap[] = { 
	REG_RESERVED(QS_INH_DBG),

};



static const u32 vsc9953_s2_regmap[] = {

	REG(S2_CORE_UPDATE_CTRL,		0x000000),

	REG(S2_CORE_MV_CFG,			0x000004),

	REG(S2_CACHE_ENTRY_DAT,			0x000008),

	REG(S2_CACHE_MASK_DAT,			0x000108),

	REG(S2_CACHE_ACTION_DAT,		0x000208),

	REG(S2_CACHE_CNT_DAT,			0x000308),

	REG(S2_CACHE_TG_DAT,			0x000388),

static const u32 vsc9953_vcap_regmap[] = {

	/* VCAP_CORE_CFG */

	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),

	REG(VCAP_CORE_MV_CFG,			0x000004),

	/* VCAP_CORE_CACHE */

	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),

	REG(VCAP_CACHE_MASK_DAT,		0x000108),

	REG(VCAP_CACHE_ACTION_DAT,		0x000208),

	REG(VCAP_CACHE_CNT_DAT,			0x000308),

	REG(VCAP_CACHE_TG_DAT,			0x000388),

};



static const u32 vsc9953_qsys_regmap[] = {
@@ -352,7 +354,7 @@ static const u32 *vsc9953_regmap[TARGET_MAX] = { 
	[QSYS]		= vsc9953_qsys_regmap,

	[REW]		= vsc9953_rew_regmap,

	[SYS]		= vsc9953_sys_regmap,

	[S2]		= vsc9953_s2_regmap,

	[S2]		= vsc9953_vcap_regmap,

	[GCB]		= vsc9953_gcb_regmap,

	[DEV_GMII]	= vsc9953_dev_gmii_regmap,

};
@@ -706,6 +708,9 @@ static const struct vcap_props vsc9953_vcap_props[] = { 
		},

		.counter_words = 4,

		.counter_width = 32,

		.target = S2,

		.keys = vsc9953_vcap_is2_keys,

		.actions = vsc9953_vcap_is2_actions,

	},

};
@@ -1031,8 +1036,6 @@ static const struct felix_info seville_info_vsc9953 = { 
	.ops			= &vsc9953_ops,

	.stats_layout		= vsc9953_stats_layout,

	.num_stats		= ARRAY_SIZE(vsc9953_stats_layout),

	.vcap_is2_keys		= vsc9953_vcap_is2_keys,

	.vcap_is2_actions	= vsc9953_vcap_is2_actions,

	.vcap			= vsc9953_vcap_props,

	.shared_queue_sz	= 2048 * 1024,

	.num_mact_rows		= 2048,

drivers/net/ethernet/mscc/ocelot_s2.h

deleted100644 → 0
+0 −64
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/* Microsemi Ocelot Switch driver

 * Copyright (c) 2018 Microsemi Corporation

 */



#ifndef _OCELOT_S2_CORE_H_

#define _OCELOT_S2_CORE_H_



#define S2_CORE_UPDATE_CTRL_UPDATE_CMD(x)      (((x) << 22) & GENMASK(24, 22))

#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_M       GENMASK(24, 22)

#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_X(x)    (((x) & GENMASK(24, 22)) >> 22)

#define S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS   BIT(21)

#define S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS  BIT(20)

#define S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS     BIT(19)

#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR(x)     (((x) << 3) & GENMASK(18, 3))

#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_M      GENMASK(18, 3)

#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x)   (((x) & GENMASK(18, 3)) >> 3)

#define S2_CORE_UPDATE_CTRL_UPDATE_SHOT        BIT(2)

#define S2_CORE_UPDATE_CTRL_CLEAR_CACHE        BIT(1)

#define S2_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN     BIT(0)



#define S2_CORE_MV_CFG_MV_NUM_POS(x)           (((x) << 16) & GENMASK(31, 16))

#define S2_CORE_MV_CFG_MV_NUM_POS_M            GENMASK(31, 16)

#define S2_CORE_MV_CFG_MV_NUM_POS_X(x)         (((x) & GENMASK(31, 16)) >> 16)

#define S2_CORE_MV_CFG_MV_SIZE(x)              ((x) & GENMASK(15, 0))

#define S2_CORE_MV_CFG_MV_SIZE_M               GENMASK(15, 0)



#define S2_CACHE_ENTRY_DAT_RSZ                 0x4



#define S2_CACHE_MASK_DAT_RSZ                  0x4



#define S2_CACHE_ACTION_DAT_RSZ                0x4



#define S2_CACHE_CNT_DAT_RSZ                   0x4



#define S2_STICKY_VCAP_ROW_DELETED_STICKY      BIT(0)



#define S2_BIST_CTRL_TCAM_BIST                 BIT(1)

#define S2_BIST_CTRL_TCAM_INIT                 BIT(0)



#define S2_BIST_CFG_TCAM_BIST_SOE_ENA          BIT(8)

#define S2_BIST_CFG_TCAM_HCG_DIS               BIT(7)

#define S2_BIST_CFG_TCAM_CG_DIS                BIT(6)

#define S2_BIST_CFG_TCAM_BIAS(x)               ((x) & GENMASK(5, 0))

#define S2_BIST_CFG_TCAM_BIAS_M                GENMASK(5, 0)



#define S2_BIST_STAT_BIST_RT_ERR               BIT(15)

#define S2_BIST_STAT_BIST_PENC_ERR             BIT(14)

#define S2_BIST_STAT_BIST_COMP_ERR             BIT(13)

#define S2_BIST_STAT_BIST_ADDR_ERR             BIT(12)

#define S2_BIST_STAT_BIST_BL1E_ERR             BIT(11)

#define S2_BIST_STAT_BIST_BL1_ERR              BIT(10)

#define S2_BIST_STAT_BIST_BL0E_ERR             BIT(9)

#define S2_BIST_STAT_BIST_BL0_ERR              BIT(8)

#define S2_BIST_STAT_BIST_PH1_ERR              BIT(7)

#define S2_BIST_STAT_BIST_PH0_ERR              BIT(6)

#define S2_BIST_STAT_BIST_PV1_ERR              BIT(5)

#define S2_BIST_STAT_BIST_PV0_ERR              BIT(4)

#define S2_BIST_STAT_BIST_RUN                  BIT(3)

#define S2_BIST_STAT_BIST_ERR                  BIT(2)

#define S2_BIST_STAT_BIST_BUSY                 BIT(1)

#define S2_BIST_STAT_TCAM_RDY                  BIT(0)



#endif /* _OCELOT_S2_CORE_H_ */

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