mlxsw: reg: Add Port Module Type Mapping Register (a513b1a5) · Commits · 戴 / test

drivers/net/ethernet/mellanox/mlxsw/reg.h

+50 −0

Original line number	Diff line number	Diff line
		@@ -5375,6 +5375,55 @@ static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
		MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
		}

		/* PMTM - Port Module Type Mapping Register
		* ----------------------------------------
		* The PMTM allows query or configuration of module types.
		*/
		#define MLXSW_REG_PMTM_ID 0x5067
		#define MLXSW_REG_PMTM_LEN 0x10

		MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);

		/* reg_pmtm_module
		* Module number.
		* Access: Index
		*/
		MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);

		enum mlxsw_reg_pmtm_module_type {
		/* Backplane with 4 lanes */
		MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
		/* QSFP */
		MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP,
		/* SFP */
		MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP,
		/* Backplane with single lane */
		MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
		/* Backplane with two lane */
		MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
		/* Chip2Chip */
		MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10,
		};

		/* reg_pmtm_module_type
		* Module type.
		* Access: RW
		*/
		MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);

		static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)
		{
		MLXSW_REG_ZERO(pmtm, payload);
		mlxsw_reg_pmtm_module_set(payload, module);
		}

		static inline void
		mlxsw_reg_pmtm_unpack(char *payload,
		enum mlxsw_reg_pmtm_module_type *module_type)
		{
		*module_type = mlxsw_reg_pmtm_module_type_get(payload);
		}

		/* HTGT - Host Trap Group Table
		* ----------------------------
		* Configures the properties for forwarding to CPU.
		@@ -10545,6 +10594,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
		MLXSW_REG(pbmc),
		MLXSW_REG(pspa),
		MLXSW_REG(pplr),
		MLXSW_REG(pmtm),
		MLXSW_REG(htgt),
		MLXSW_REG(hpkt),
		MLXSW_REG(rgcr),

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