Commit 94e76837 authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller
Browse files

mlxsw: reg: Extend PMLP tx/rx lane value size to 4 bits 



The tx/rx lane fields got extended to 4 bits, update the reg field
description accordingly.

Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Reviewed-by: default avatarShalom Toledo <shalomt@mellanox.com>
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d74361dc

drivers/net/ethernet/mellanox/mlxsw/reg.h

+3 −2
Original line number Diff line number Diff line
@@ -3969,6 +3969,7 @@ MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 
 * 1 - Lane 0 is used.

 * 2 - Lanes 0 and 1 are used.

 * 4 - Lanes 0, 1, 2 and 3 are used.

 * 8 - Lanes 0-7 are used.

 * Access: RW

 */

MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
@@ -3983,14 +3984,14 @@ MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 
 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);



/* reg_pmlp_rx_lane

 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is

 * equal to Tx lane.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);



static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)

{

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