Commit a49ba41c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v5.1-rockchip-clk1' of... 

Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.

* tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328
parents bfeffd15 491b00ff

drivers/clk/rockchip/clk-rk3188.c

+2 −2
Original line number Diff line number Diff line
@@ -586,12 +586,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 
	COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,

			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,

			RK2928_CLKGATE_CON(3), 1, GFLAGS),

	MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,

	MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),

	COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,

			RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,

			RK2928_CLKGATE_CON(3), 2, GFLAGS),

	MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,

	MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),



	COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,

drivers/clk/rockchip/clk-rk3328.c

+6 −6
Original line number Diff line number Diff line
@@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = { 


static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {

	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */

	RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),

	RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),

	/* vco = 1016064000 */

	RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),

	RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),

	/* vco = 983040000 */

	RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),

	RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),

	/* vco = 983040000 */

	RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),

	RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),

	/* vco = 860156000 */

	RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),

	RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),

	/* vco = 903168000 */

	RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),

	RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),

	/* vco = 819200000 */

	{ /* sentinel */ },

};

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