Commit 491b00ff authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks 



Add CLK_SET_RATE_PARENT for both rk3066 lcdc dclk.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarJohan Jonker <jbx6244@gmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent a0e447b0

drivers/clk/rockchip/clk-rk3188.c

+2 −2
Original line number Diff line number Diff line
@@ -586,12 +586,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 
	COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,

			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,

			RK2928_CLKGATE_CON(3), 1, GFLAGS),

	MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,

	MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),

	COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,

			RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,

			RK2928_CLKGATE_CON(3), 2, GFLAGS),

	MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,

	MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),



	COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,

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