Commit a339bdf6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and 'clk-imx6sll' into clk-next 

* clk-stratix10:
  clk: socfpga: stratix10: add clock driver for Stratix10 platform
  dt-bindings: documentation: add clock bindings information for Stratix10

* clk-imx:
  clk: imx7d: Move clks_init_on before any clock operations
  clk: imx7d: Correct ahb clk parent select
  clk: imx7d: Correct dram pll type
  clk: imx7d: Add USB clock information
  clk: imx: pllv2: avoid using uninitialized values
  clk: imx6ull: Add epdc_podf instead of sim_podf
  clk: imx: imx7d: correct video pll clock tree
  clk: imx: imx7d: add the Keypad Port module clock
  clk: imx7d: add CAAM clock
  clk: imx: imx7d: add the snvs clock
  clk: imx: imx6sx: update cko mux options

* clk-bcm:
  clk: bcm2835: De-assert/assert PLL reset signal when appropriate

* clk-cs2000:
  clk: cs2000: set pm_ops in hibernate-compatible way

* clk-imx6sll:
  clk: imx: add clock driver for imx6sll
  dt-bindings: imx: update clock doc for imx6sll
  clk: imx: add new gate/gate2 wrapper funtion
  clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
parents a83fdfae 07afb8db 8d41e653 75387237 eade4ccd 4a5f720b

Documentation/devicetree/bindings/clock/imx6sll-clock.txt

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* Clock bindings for Freescale i.MX6 SLL



Required properties:

- compatible: Should be "fsl,imx6sll-ccm"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- clocks: list of clock specifiers, must contain an entry for each required

  entry in clock-names

- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sll-clock.h

for the full list of i.MX6 SLL clock IDs.



Examples:



#include <dt-bindings/clock/imx6sll-clock.h>



clks: clock-controller@20c4000 {

		compatible = "fsl,imx6sll-ccm";

		reg = <0x020c4000 0x4000>;

		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;

		#clock-cells = <1>;

		clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;

		clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";

};



uart1: serial@2020000 {

		compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";

		reg = <0x02020000 0x4000>;

		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks IMX6SLL_CLK_UART1_IPG>,

			 <&clks IMX6SLL_CLK_UART1_SERIAL>;

		clock-names = "ipg", "per";

};

Documentation/devicetree/bindings/clock/intc_stratix10.txt

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Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be

	"intel,stratix10-clkmgr"



- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.



- #clock-cells : from common clock binding, shall be set to 1.



Example:

	clkmgr: clock-controller@ffd10000 {

		compatible = "intel,stratix10-clkmgr";

		reg = <0xffd10000 0x1000>;

		#clock-cells = <1>;

	};

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 
obj-$(CONFIG_PLAT_SPEAR)		+= spear/

obj-$(CONFIG_ARCH_SPRD)			+= sprd/

obj-$(CONFIG_ARCH_STI)			+= st/

obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi-ng/

obj-$(CONFIG_ARCH_TEGRA)		+= tegra/

drivers/clk/bcm/clk-bcm2835.c

+5 −3
Original line number Diff line number Diff line
@@ -602,9 +602,7 @@ static void bcm2835_pll_off(struct clk_hw *hw) 
	const struct bcm2835_pll_data *data = pll->data;



	spin_lock(&cprman->regs_lock);

	cprman_write(cprman, data->cm_ctrl_reg,

		     cprman_read(cprman, data->cm_ctrl_reg) |

		     CM_PLL_ANARST);

	cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);

	cprman_write(cprman, data->a2w_ctrl_reg,

		     cprman_read(cprman, data->a2w_ctrl_reg) |

		     A2W_PLL_CTRL_PWRDN);
@@ -638,6 +636,10 @@ static int bcm2835_pll_on(struct clk_hw *hw) 
		cpu_relax();

	}



	cprman_write(cprman, data->a2w_ctrl_reg,

		     cprman_read(cprman, data->a2w_ctrl_reg) |

		     A2W_PLL_CTRL_PRST_DISABLE);



	return 0;

}

drivers/clk/clk-cs2000-cp.c

+1 −1
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@@ -549,7 +549,7 @@ static int cs2000_resume(struct device *dev) 
}



static const struct dev_pm_ops cs2000_pm_ops = {

	.resume_early	= cs2000_resume,

	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)

};



static struct i2c_driver cs2000_driver = {

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