Commit a83fdfae authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and... 

Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and 'clk-ti-flag-fix' into clk-next

* clk-davinci:
  clk: davinci: Remove redundant dev_err calls
  clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
  clk: davinci: New driver for TI DA8XX CFGCHIP clocks
  dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks
  clk: davinci: Add platform information for TI DM646x PSC
  clk: davinci: Add platform information for TI DM644x PSC
  clk: davinci: Add platform information for TI DM365 PSC
  clk: davinci: Add platform information for TI DM355 PSC
  clk: davinci: Add platform information for TI DA850 PSC
  clk: davinci: Add platform information for TI DA830 PSC
  clk: davinci: New driver for davinci PSC clocks
  dt-bindings: clock: New bindings for TI Davinci PSC
  clk: davinci: Add platform information for TI DM646x PLL
  clk: davinci: Add platform information for TI DM644x PLL
  clk: davinci: Add platform information for TI DM365 PLL
  clk: davinci: Add platform information for TI DM355 PLL
  clk: davinci: Add platform information for TI DA850 PLL
  clk: davinci: Add platform information for TI DA830 PLL
  clk: davinci: New driver for davinci PLL clocks
  dt-bindings: clock: Add new bindings for TI Davinci PLL clocks

* clk-si544:
  clk: Add driver for the si544 clock generator chip

* clk-rockchip:
  clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
  clk: rockchip: Fix error return in phase clock registration
  clk: rockchip: Correct the behaviour of restoring cached phase
  clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
  clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
  clk: rockchip: Add 1.6GHz PLL rate for rk3399
  clk: rockchip: Restore the clock phase after the rate was changed
  clk: rockchip: Prevent calculating mmc phase if clock rate is zero
  clk: rockchip: Free the memory on the error path
  clk: rockchip: document hdmi_phy external input for rk3328
  clk: rockchip: add flags for rk3328 dclk_lcdc
  clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
  clk: rockchip: protect all remaining rk3328 interconnect clocks
  clk: rockchip: export sclk_hdmi_sfc on rk3328
  clk: rockchip: remove HCLK_VIO from rk3328 dt header
  clk: rockchip: fix hclk_vio_niu on rk3328

* clk-uniphier:
  clk: uniphier: add additional ethernet clock lines for Pro4
  clk: uniphier: add SATA clock control support
  clk: uniphier: add PCIe clock control support
  clk: uniphier: add ethernet clock control support for PXs3
  clk: uniphier: add Pro4/Pro5/PXs2 audio system clock

* clk-ti-flag-fix:
  clk: ti: fix flag space conflict with clkctrl clocks
  clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
parents b0378192 fc3fcb4f 953cc3e8 f6ae7c36 6f1aa4ef 269bd202

Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt

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@@ -32,6 +32,7 @@ clock-output-names: 
 - "clkin_i2s" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional

 - "phy_50m_out" - output clock of the pll in the mac phy

 - "hdmi_phy" - output clock of the hdmi phy pll - optional



Example: Clock controller node:

Documentation/devicetree/bindings/clock/silabs,si544.txt

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Binding for Silicon Labs 544 programmable I2C clock generator.



Reference

This binding uses the common clock binding[1]. Details about the device can be

found in the datasheet[2].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Si544 datasheet

    https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf



Required properties:

 - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according

               to the speed grade of the chip.

 - reg: I2C device address.

 - #clock-cells: From common clock bindings: Shall be 0.



Optional properties:

 - clock-output-names: From common clock bindings. Recommended to be "si544".



Example:

	si544: clock-controller@55 {

		reg = <0x55>;

		#clock-cells = <0>;

		compatible = "silabs,si544b";

	};

Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt

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Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks



TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of

registers call CFGCHIPn. Some of these registers function as clock

gates. This document describes the bindings for those clocks.



All of the clock nodes described below must be child nodes of a CFGCHIP node

(compatible = "ti,da830-cfgchip").



USB PHY clocks

--------------

Required properties:

- compatible: shall be "ti,da830-usb-phy-clocks".

- #clock-cells: from common clock binding; shall be set to 1.

- clocks: phandles to the parent clocks corresponding to clock-names

- clock-names: shall be "fck", "usb_refclkin", "auxclk"



This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz

clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.



eHRPWM Time Base Clock (TBCLK)

------------------------------

Required properties:

- compatible: shall be "ti,da830-tbclksync".

- #clock-cells: from common clock binding; shall be set to 0.

- clocks: phandle to the parent clock

- clock-names: shall be "fck"



PLL DIV4.5 divider

------------------

Required properties:

- compatible: shall be "ti,da830-div4p5ena".

- #clock-cells: from common clock binding; shall be set to 0.

- clocks: phandle to the parent clock

- clock-names: shall be "pll0_pllout"



EMIFA clock source (ASYNC1)

---------------------------

Required properties:

- compatible: shall be "ti,da850-async1-clksrc".

- #clock-cells: from common clock binding; shall be set to 0.

- clocks: phandles to the parent clocks corresponding to clock-names

- clock-names: shall be "pll0_sysclk3", "div4.5"



ASYNC3 clock source

-------------------

Required properties:

- compatible: shall be "ti,da850-async3-clksrc".

- #clock-cells: from common clock binding; shall be set to 0.

- clocks: phandles to the parent clocks corresponding to clock-names

- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"



Examples:



	cfgchip: syscon@1417c {

		compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";

		reg = <0x1417c 0x14>;



		usb_phy_clk: usb-phy-clocks {

			compatible = "ti,da830-usb-phy-clocks";

			#clock-cells = <1>;

			clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;

			clock-names = "fck", "usb_refclkin", "auxclk";

		};

		ehrpwm_tbclk: ehrpwm_tbclk {

			compatible = "ti,da830-tbclksync";

			#clock-cells = <0>;

			clocks = <&psc1 17>;

			clock-names = "fck";

		};

		div4p5_clk: div4.5 {

			compatible = "ti,da830-div4p5ena";

			#clock-cells = <0>;

			clocks = <&pll0_pllout>;

			clock-names = "pll0_pllout";

		};

		async1_clk: async1 {

			compatible = "ti,da850-async1-clksrc";

			#clock-cells = <0>;

			clocks = <&pll0_sysclk 3>, <&div4p5_clk>;

			clock-names = "pll0_sysclk3", "div4.5";

		};

		async3_clk: async3 {

			compatible = "ti,da850-async3-clksrc";

			#clock-cells = <0>;

			clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;

			clock-names = "pll0_sysclk2", "pll1_sysclk2";

		};

	};



Also see:

- Documentation/devicetree/bindings/clock/clock-bindings.txt

Documentation/devicetree/bindings/clock/ti/davinci/pll.txt

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Binding for TI DaVinci PLL Controllers



The PLL provides clocks to most of the components on the SoC. In addition

to the PLL itself, this controller also contains bypasses, gates, dividers,

an multiplexers for various clock signals.



Required properties:

- compatible: shall be one of:

	- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX

	- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX

- reg: physical base address and size of the controller's register area.

- clocks: phandles corresponding to the clock names

- clock-names: names of the clock sources - depends on compatible string

	- for "ti,da850-pll0", shall be "clksrc", "extclksrc"

	- for "ti,da850-pll1", shall be "clksrc"



Optional properties:

- ti,clkmode-square-wave: Indicates that the the board is supplying a square

	wave input on the OSCIN pin instead of using a crystal oscillator.

	This property is only valid when compatible = "ti,da850-pll0".





Optional child nodes:



pllout

	Describes the main PLL clock output (before POSTDIV). The node name must

	be "pllout".



	Required properties:

	- #clock-cells: shall be 0



sysclk

	Describes the PLLDIVn divider clocks that provide the SYSCLKn clock

	domains. The node name must be "sysclk". Consumers of this node should

	use "n" in "SYSCLKn" as the index parameter for the clock cell.



	Required properties:

	- #clock-cells: shall be 1



auxclk

	Describes the AUXCLK output of the PLL. The node name must be "auxclk".

	This child node is only valid when compatible = "ti,da850-pll0".



	Required properties:

	- #clock-cells: shall be 0



obsclk

	Describes the OBSCLK output of the PLL. The node name must be "obsclk".



	Required properties:

	- #clock-cells: shall be 0





Examples:



	pll0: clock-controller@11000 {

		compatible = "ti,da850-pll0";

		reg = <0x11000 0x1000>;

		clocks = <&ref_clk>, <&pll1_sysclk 3>;

		clock-names = "clksrc", "extclksrc";

		ti,clkmode-square-wave;



		pll0_pllout: pllout {

			#clock-cells = <0>;

		};



		pll0_sysclk: sysclk {

			#clock-cells = <1>;

		};



		pll0_auxclk: auxclk {

			#clock-cells = <0>;

		};



		pll0_obsclk: obsclk {

			#clock-cells = <0>;

		};

	};



	pll1: clock-controller@21a000 {

		compatible = "ti,da850-pll1";

		reg = <0x21a000 0x1000>;

		clocks = <&ref_clk>;

		clock-names = "clksrc";



		pll0_sysclk: sysclk {

			#clock-cells = <1>;

		};



		pll0_obsclk: obsclk {

			#clock-cells = <0>;

		};

	};



Also see:

- Documentation/devicetree/bindings/clock/clock-bindings.txt

Documentation/devicetree/bindings/clock/ti/davinci/psc.txt

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Binding for TI DaVinci Power Sleep Controller (PSC)



The PSC provides power management, clock gating and reset functionality. It is

primarily used for clocking.



Required properties:

- compatible: shall be one of:

	- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX

	- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX

- reg: physical base address and size of the controller's register area

- #clock-cells: from common clock binding; shall be set to 1

- #power-domain-cells: from generic power domain binding; shall be set to 1.

- clocks: phandles to clocks corresponding to the clock-names property

- clock-names: list of parent clock names - depends on compatible value

	- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",

	  "pll0_sysclk4", "pll0_sysclk6", "async1"

	- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"



Optional properties:

- #reset-cells: from reset binding; shall be set to 1 - only applicable when

  at least one local domain provides a local reset.



Consumers:



	Clock, power domain and reset consumers shall use the local power domain

	module ID (LPSC) as the index corresponding to the clock cell. Refer to

	the device-specific datasheet to find these numbers. NB: Most local

	domains	only provide a clock/power domain and not a reset.



Examples:



	psc0: clock-controller@10000 {

		compatible = "ti,da850-psc0";

		reg = <0x10000 0x1000>;

		#clock-cells = <1>;

		#power-domain-cells = <1>;

		#reset-cells = <1>;

		clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,

			 <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;

		clock_names = "pll0_sysclk1", "pll0_sysclk2",

			      "pll0_sysclk4", "pll0_sysclk6", "async1";

	};

	psc1: clock-controller@227000 {

		compatible = "ti,da850-psc1";

		reg = <0x227000 0x1000>;

		#clock-cells = <1>;

		#power-domain-cells = <1>;

		clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;

		clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";

	};



	/* consumer */

	dsp: dsp@11800000 {

		compatible = "ti,da850-dsp";

		reg = <0x11800000 0x40000>,

		      <0x11e00000 0x8000>,

		      <0x11f00000 0x8000>,

		      <0x01c14044 0x4>,

		      <0x01c14174 0x8>;

		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";

		interrupt-parent = <&intc>;

		interrupts = <28>;

		clocks = <&psc0 15>;

		power-domains = <&psc0 15>;

		resets = <&psc0 15>;

	};



Also see:

- Documentation/devicetree/bindings/clock/clock-bindings.txt

- Documentation/devicetree/bindings/power/power_domain.txt

- Documentation/devicetree/bindings/reset/reset.txt

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