Merge branches 'pci/misc', 'pci/pm', 'pci/host-designware', 'pci/host-imx6',...

Optional properties:

- reset-gpio: gpio pin number of power good signal

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

  specify this property, to keep backwards compatibility a range of 0x00-0xff

  is assumed if not present)

TI Keystone PCIe interface

Keystone PCI host Controller is based on Designware PCI h/w version 3.65.

It shares common functions with PCIe Designware core driver and inherit

common properties defined in

Documentation/devicetree/bindings/pci/designware-pci.txt

Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt

for the details of Designware DT bindings.  Additional properties are

described here as well as properties that are not applicable.

Required Properties:-

compatibility: "ti,keystone-pcie"

reg:	index 1 is the base address and length of DW application registers.

	index 2 is the base address and length of PCI mode configuration

	register.

	index 3 is the base address and length of PCI device ID register.

pcie_msi_intc : Interrupt controller device node for MSI IRQ chip

	interrupt-cells: should be set to 1

	interrupt-parent: Parent interrupt controller phandle

	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines

 Example:

	pcie_msi_intc: msi-interrupt-controller {

			interrupt-controller;

			#interrupt-cells = <1>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,

					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;

	};

pcie_intc: Interrupt controller device node for Legacy IRQ chip

	interrupt-cells: should be set to 1

	interrupt-parent: Parent interrupt controller phandle

	interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines

 Example:

	pcie_intc: legacy-interrupt-controller {

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;

	};

Optional properties:-

	phys: phandle to Generic Keystone SerDes phy for PCI

	phy-names: name of the Generic Keystine SerDes phy for PCI

	  - If boot loader already does PCI link establishment, then phys and

	    phy-names shouldn't be present.

Designware DT Properties not applicable for Keystone PCI

1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.

Note for PCI driver usage

=========================

Driver requires pci=pcie_bus_perf in the bootargs for proper functioning.

* Xilinx AXI PCIe Root Port Bridge DT description

Required properties:

- #address-cells: Address representation for root ports, set to <3>

- #size-cells: Size representation for root ports, set to <2>

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"

- reg: Should contain AXI PCIe registers location and length

- device_type: must be "pci"

- interrupts: Should contain AXI PCIe interrupt

- interrupt-map-mask,

  interrupt-map: standard PCI properties to define the mapping of the

	PCI interface to interrupt numbers.

- ranges: ranges for the PCI memory regions (I/O space region is not

	supported by hardware)

	Please refer to the standard PCI bus binding document for a more

	detailed explanation

Optional properties:

- bus-range: PCI bus numbers covered

Interrupt controller child node

+++++++++++++++++++++++++++++++

Required properties:

- interrupt-controller: identifies the node as an interrupt controller

- #address-cells: specifies the number of cells needed to encode an

	address. The value must be 0.

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

NOTE:

The core provides a single interrupt for both INTx/MSI messages. So,

created a interrupt controller node to support 'interrupt-map' DT

functionality.  The driver will create an IRQ domain for this map, decode

the four INTx interrupts in ISR and route them to this domain.

Example:

++++++++

	pci_express: axi-pcie@50000000 {

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		compatible = "xlnx,axi-pcie-host-1.00.a";

		reg = < 0x50000000 0x10000000 >;

		device_type = "pci";

		interrupts = < 0 52 4 >;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc 1>,

				<0 0 0 2 &pcie_intc 2>,

				<0 0 0 3 &pcie_intc 3>,

				<0 0 0 4 &pcie_intc 4>;

		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;

		pcie_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		}

	};

IO region

  devm_release_mem_region()

  devm_release_region()

  devm_release_resource()

  devm_request_mem_region()

  devm_request_region()

  devm_request_resource()

IOMAP

  devm_ioport_map()

PCI DRIVER FOR IMX6

M:	Richard Zhu <r65037@freescale.com>

M:	Shawn Guo <shawn.guo@freescale.com>

M:	Lucas Stach <l.stach@pengutronix.de>

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/pci/host/*imx6*

PCI DRIVER FOR TI KEYSTONE

M:	Murali Karicheri <m-karicheri2@ti.com>

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/pci/host/*keystone*

PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)

M:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

M:	Jason Cooper <jason@lakedaemon.net>