Commit a10f361d authored by Jani Nikula's avatar Jani Nikula
Browse files

Revert "drm/i915: Expand subslice mask" 

This reverts commit 1ac159e2 ("drm/i915: Expand subslice mask"),
which kills ICL due to GEM_BUG_ON() sanity checks before CI even gets a
chance to do anything.

The commit exposes an issue in commit 1e40d4ae ("drm/i915/cnl:
Implement WaProgramMgsrForCorrectSliceSpecificMmioReads"), which will
also need to be addressed.

There's a proposed fix [1], but considering the seeming uncertainty with
the fix as well as the size of the regressing commit (in this context,
the one that actually brings down ICL), this warrants a revert to get
ICL working, and gives us time to get all of this right without
rushing. Even if this means shooting the messenger.

<3>[    9.426327] intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
<4>[    9.426355] ------------[ cut here ]------------
<2>[    9.426357] kernel BUG at drivers/gpu/drm/i915/gt/intel_sseu.c:46!
<4>[    9.426371] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI
<4>[    9.426377] CPU: 1 PID: 364 Comm: systemd-udevd Not tainted 5.2.0-rc2-CI-CI_DRM_6159+ #1
<4>[    9.426385] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3183.A00.1905020411 05/02/2019
<4>[    9.426444] RIP: 0010:intel_sseu_get_subslices+0x8a/0xe0 [i915]
<4>[    9.426452] Code: d5 76 b7 e0 48 8b 35 9d 24 21 00 49 c7 c0 07 f0 72 a0 b9 2e 00 00 00 48 c7 c2 00 8e 6d a0 48 c7 c7 a5 14 5b a0 e8 36 3c be e0 <0f> 0b 48 c7 c1 80 d5 6f a0 ba 30 00 00 00 48 c7 c6 00 8e 6d a0 48
<4>[    9.426468] RSP: 0018:ffffc9000037b9c8 EFLAGS: 00010282
<4>[    9.426475] RAX: 000000000000000f RBX: 0000000000000000 RCX: 0000000000000000
<4>[    9.426482] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffff88849e346f98
<4>[    9.426490] RBP: ffff88848a200000 R08: 0000000000000004 R09: ffff88849d50b000
<4>[    9.426497] R10: 0000000000000000 R11: ffff88849e346f98 R12: ffff88848a209e78
<4>[    9.426505] R13: 0000000003000000 R14: ffff88848a20b1a8 R15: 0000000000000000
<4>[    9.426513] FS:  00007f73d5ae8680(0000) GS:ffff88849fc80000(0000) knlGS:0000000000000000
<4>[    9.426521] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[    9.426527] CR2: 0000561417b01260 CR3: 0000000494764003 CR4: 0000000000760ee0
<4>[    9.426535] PKRU: 55555554
<4>[    9.426538] Call Trace:
<4>[    9.426585]  wa_init_mcr+0xd5/0x110 [i915]
<4>[    9.426597]  ? lock_acquire+0xa6/0x1c0
<4>[    9.426645]  icl_gt_workarounds_init+0x21/0x1a0 [i915]
<4>[    9.426694]  ? i915_driver_load+0xfcf/0x18a0 [i915]
<4>[    9.426739]  gt_init_workarounds+0x14c/0x230 [i915]
<4>[    9.426748]  ? _raw_spin_unlock_irq+0x24/0x50
<4>[    9.426789]  intel_gt_init_workarounds+0x1b/0x30 [i915]
<4>[    9.426835]  i915_driver_load+0xfd7/0x18a0 [i915]
<4>[    9.426843]  ? lock_acquire+0xa6/0x1c0
<4>[    9.426850]  ? __pm_runtime_resume+0x4f/0x80
<4>[    9.426857]  ? _raw_spin_unlock_irqrestore+0x4c/0x60
<4>[    9.426863]  ? _raw_spin_unlock_irqrestore+0x4c/0x60
<4>[    9.426870]  ? lockdep_hardirqs_on+0xe3/0x1b0
<4>[    9.426915]  i915_pci_probe+0x29/0xa0 [i915]
<4>[    9.426923]  pci_device_probe+0x9e/0x120
<4>[    9.426930]  really_probe+0xea/0x3c0
<4>[    9.426936]  driver_probe_device+0x10b/0x120
<4>[    9.426942]  device_driver_attach+0x4a/0x50
<4>[    9.426948]  __driver_attach+0x97/0x130
<4>[    9.426954]  ? device_driver_attach+0x50/0x50
<4>[    9.426960]  bus_for_each_dev+0x74/0xc0
<4>[    9.426966]  bus_add_driver+0x13f/0x210
<4>[    9.426971]  ? 0xffffffffa083b000
<4>[    9.426976]  driver_register+0x56/0xe0
<4>[    9.426982]  ? 0xffffffffa083b000
<4>[    9.426987]  do_one_initcall+0x58/0x300
<4>[    9.426994]  ? do_init_module+0x1d/0x1f6
<4>[    9.427001]  ? rcu_read_lock_sched_held+0x6f/0x80
<4>[    9.427007]  ? kmem_cache_alloc_trace+0x261/0x290
<4>[    9.427014]  do_init_module+0x56/0x1f6
<4>[    9.427020]  load_module+0x24d1/0x2990
<4>[    9.427032]  ? __se_sys_finit_module+0xd3/0xf0
<4>[    9.427037]  __se_sys_finit_module+0xd3/0xf0
<4>[    9.427047]  do_syscall_64+0x55/0x1c0
<4>[    9.427053]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[    9.427059] RIP: 0033:0x7f73d5609839
<4>[    9.427064] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
<4>[    9.427082] RSP: 002b:00007ffdf34477b8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
<4>[    9.427091] RAX: ffffffffffffffda RBX: 00005559fd5d7b40 RCX: 00007f73d5609839
<4>[    9.427099] RDX: 0000000000000000 RSI: 00007f73d52e8145 RDI: 000000000000000f
<4>[    9.427106] RBP: 00007f73d52e8145 R08: 0000000000000000 R09: 00007ffdf34478d0
<4>[    9.427114] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
<4>[    9.427121] R13: 00005559fd5c90f0 R14: 0000000000020000 R15: 00005559fd5d7b40
<4>[    9.427131] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel crct10dif_pclmul crc32_pclmul snd_hda_codec snd_hwdep e1000e snd_hda_core ghash_clmulni_intel ptp snd_pcm cdc_ether usbnet mii pps_core mei_me mei prime_numbers btusb btrtl btbcm btintel bluetooth ecdh_generic ecc
<4>[    9.427254] ---[ end trace af3eeb543bd66e66 ]---

[1] http://patchwork.freedesktop.org/patch/msgid/20190528200655.11605-1-chris@chris-wilson.co.uk

References: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/fi-icl-u2/pstore0-1517155098_Oops_1.log


References: 1e40d4ae ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
Fixes: 1ac159e2 ("drm/i915: Expand subslice mask")
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Yunwei Zhang <yunwei.zhang@intel.com>
Acked-by: default avatarDaniel Vetter <daniel@ffwll.ch>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-jani.nikula@intel.com
parent 0c1f8457

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+2 −22
Original line number Diff line number Diff line
@@ -953,30 +953,12 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 
	}

}



static inline u32

intel_sseu_fls_subslice(const struct sseu_dev_info *sseu, u32 slice)

{

	u32 subslice;

	int i;



	for (i = sseu->ss_stride - 1; i >= 0; i--) {

		subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride +

						   i]);

		if (subslice) {

			subslice += i * BITS_PER_BYTE;

			break;

		}

	}



	return subslice;

}



u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)

{

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	u32 mcr_s_ss_select;

	u32 slice = fls(sseu->slice_mask);

	u32 subslice = intel_sseu_fls_subslice(sseu, slice);

	u32 subslice = fls(sseu->subslice_mask[slice]);



	if (IS_GEN(dev_priv, 10))

		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -1052,7 +1034,6 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, 
			       struct intel_instdone *instdone)

{

	struct drm_i915_private *dev_priv = engine->i915;

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	struct intel_uncore *uncore = engine->uncore;

	u32 mmio_base = engine->mmio_base;

	int slice;
@@ -1070,8 +1051,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, 


		instdone->slice_common =

			intel_uncore_read(uncore, GEN7_SC_INSTDONE);

		for_each_instdone_slice_subslice(dev_priv, sseu, slice,

						 subslice) {

		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

			instdone->sampler[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_SAMPLER_INSTDONE);

drivers/gpu/drm/i915/gt/intel_engine_types.h

+15 −15
Original line number Diff line number Diff line
@@ -552,20 +552,20 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine) 
	return engine->flags & I915_ENGINE_IS_VIRTUAL;

}



#define instdone_has_slice(dev_priv___, sseu___, slice___) \

	((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \

	BIT(slice___))



#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \

	(IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \

	 intel_sseu_has_subslice(sseu__, slice__, subslice__))



#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \

	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \

	     (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \

	     (slice_) += ((subslice_) == 0)) \

		for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \

			    (instdone_has_subslice(dev_priv_, sseu_, slice_, \

						    subslice_)))

#define instdone_slice_mask(dev_priv__) \

	(IS_GEN(dev_priv__, 7) ? \

	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)



#define instdone_subslice_mask(dev_priv__) \

	(IS_GEN(dev_priv__, 7) ? \

	 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])



#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \

	for ((slice__) = 0, (subslice__) = 0; \

	     (slice__) < I915_MAX_SLICES; \

	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \

	       (slice__) += ((subslice__) == 0)) \

		for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \

			    (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))



#endif /* __INTEL_ENGINE_TYPES_H__ */

drivers/gpu/drm/i915/gt/intel_hangcheck.c

+1 −2
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone) 
static bool subunits_stuck(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	struct intel_instdone instdone;

	struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;

	bool stuck;
@@ -73,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine) 
	stuck &= instdone_unchanged(instdone.slice_common,

				    &accu_instdone->slice_common);



	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {

	for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

		stuck &= instdone_unchanged(instdone.sampler[slice][subslice],

					    &accu_instdone->sampler[slice][subslice]);

		stuck &= instdone_unchanged(instdone.row[slice][subslice],

drivers/gpu/drm/i915/gt/intel_sseu.c

+1 −46
Original line number Diff line number Diff line
@@ -8,17 +8,6 @@ 
#include "intel_lrc_reg.h"

#include "intel_sseu.h"



void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

			 u8 max_subslices, u8 max_eus_per_subslice)

{

	sseu->max_slices = max_slices;

	sseu->max_subslices = max_subslices;

	sseu->max_eus_per_subslice = max_eus_per_subslice;



	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);

	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);

}



unsigned int

intel_sseu_subslice_total(const struct sseu_dev_info *sseu)

{
@@ -30,44 +19,10 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) 
	return total;

}



void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,

			       u8 *to_mask)

{

	int offset = slice * sseu->ss_stride;



	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);

}



u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)

{

	int i, offset = slice * sseu->ss_stride;

	u32 mask;



	GEM_BUG_ON(slice >= sseu->max_slices);



	GEM_BUG_ON(sseu->ss_stride > sizeof(mask));



	for (i = 0; i < sseu->ss_stride; i++)

		mask |= (u32)sseu->subslice_mask[offset + i] <<

			i * BITS_PER_BYTE;



	return mask;

}



void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,

			      u32 ss_mask)

{

	int i, offset = slice * sseu->ss_stride;



	for (i = 0; i < sseu->ss_stride; i++)

		sseu->subslice_mask[offset + i] =

			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;

}



unsigned int

intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)

{

	return hweight32(intel_sseu_get_subslices(sseu, slice));

	return hweight8(sseu->subslice_mask[slice]);

}



u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,

drivers/gpu/drm/i915/gt/intel_sseu.h

+1 −26
Original line number Diff line number Diff line
@@ -15,11 +15,10 @@ struct drm_i915_private; 
#define GEN_MAX_SLICES		(6) /* CNL upper bound */

#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */

#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)

#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)



struct sseu_dev_info {

	u8 slice_mask;

	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];

	u8 subslice_mask[GEN_MAX_SLICES];

	u16 eu_total;

	u8 eu_per_subslice;

	u8 min_eu_in_pool;
@@ -34,9 +33,6 @@ struct sseu_dev_info { 
	u8 max_subslices;

	u8 max_eus_per_subslice;



	u8 ss_stride;

	u8 eu_stride;



	/* We don't have more than 8 eus per subslice at the moment and as we

	 * store eus enabled using bits, no need to multiply by eus per

	 * subslice.
@@ -67,33 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 
	return value;

}



static inline bool

intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,

			int subslice)

{

	u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +

				      subslice / BITS_PER_BYTE];



	return mask & BIT(subslice % BITS_PER_BYTE);

}



void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

			 u8 max_subslices, u8 max_eus_per_subslice);



unsigned int

intel_sseu_subslice_total(const struct sseu_dev_info *sseu);



unsigned int

intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);



void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,

			       u8 *to_mask);



u32  intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);



void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,

			      u32 ss_mask);



u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,

			 const struct intel_sseu *req_sseu);

CRA Git | Maintained and supported by SUSTech CRA and CCSE