Commit 1ac159e2 authored by Stuart Summers's avatar Stuart Summers Committed by Manasi Navare
Browse files

drm/i915: Expand subslice mask 



Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
  slice * subslice stride + subslice index / 8

v2: fix spacing in set_sseu_info args
    use set_sseu_info to initialize sseu data when building
    device status in debugfs
    rename variables in intel_engine_types.h to avoid checkpatch
    warnings
v3: update headers in intel_sseu.h
v4: add const to some sseu_dev_info variables
    use sseu->eu_stride for EU stride calculations
v5: address review comments from Tvrtko and Daniele
v6: remove extra space in intel_sseu_get_subslices
    return the correct subslice enable in for_each_instdone
    add GEM_BUG_ON to ensure user doesn't pass invalid ss_mask size
    use printk formatted string for subslice mask
v7: remove string.h header and rebase

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarStuart Summers <stuart.summers@intel.com>
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190524154022.13575-6-stuart.summers@intel.com
parent 0040fd19

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+22 −2
Original line number Diff line number Diff line
@@ -953,12 +953,30 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 
	}

}



static inline u32

intel_sseu_fls_subslice(const struct sseu_dev_info *sseu, u32 slice)

{

	u32 subslice;

	int i;



	for (i = sseu->ss_stride - 1; i >= 0; i--) {

		subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride +

						   i]);

		if (subslice) {

			subslice += i * BITS_PER_BYTE;

			break;

		}

	}



	return subslice;

}



u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)

{

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	u32 mcr_s_ss_select;

	u32 slice = fls(sseu->slice_mask);

	u32 subslice = fls(sseu->subslice_mask[slice]);

	u32 subslice = intel_sseu_fls_subslice(sseu, slice);



	if (IS_GEN(dev_priv, 10))

		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -1034,6 +1052,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, 
			       struct intel_instdone *instdone)

{

	struct drm_i915_private *dev_priv = engine->i915;

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	struct intel_uncore *uncore = engine->uncore;

	u32 mmio_base = engine->mmio_base;

	int slice;
@@ -1051,7 +1070,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, 


		instdone->slice_common =

			intel_uncore_read(uncore, GEN7_SC_INSTDONE);

		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

		for_each_instdone_slice_subslice(dev_priv, sseu, slice,

						 subslice) {

			instdone->sampler[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_SAMPLER_INSTDONE);

drivers/gpu/drm/i915/gt/intel_engine_types.h

+15 −15
Original line number Diff line number Diff line
@@ -552,20 +552,20 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine) 
	return engine->flags & I915_ENGINE_IS_VIRTUAL;

}



#define instdone_slice_mask(dev_priv__) \

	(IS_GEN(dev_priv__, 7) ? \

	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)



#define instdone_subslice_mask(dev_priv__) \

	(IS_GEN(dev_priv__, 7) ? \

	 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])



#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \

	for ((slice__) = 0, (subslice__) = 0; \

	     (slice__) < I915_MAX_SLICES; \

	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \

	       (slice__) += ((subslice__) == 0)) \

		for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \

			    (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))

#define instdone_has_slice(dev_priv___, sseu___, slice___) \

	((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \

	BIT(slice___))



#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \

	(IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \

	 intel_sseu_has_subslice(sseu__, slice__, subslice__))



#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \

	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \

	     (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \

	     (slice_) += ((subslice_) == 0)) \

		for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \

			    (instdone_has_subslice(dev_priv_, sseu_, slice_, \

						    subslice_)))



#endif /* __INTEL_ENGINE_TYPES_H__ */

drivers/gpu/drm/i915/gt/intel_hangcheck.c

+2 −1
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone) 
static bool subunits_stuck(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

	struct intel_instdone instdone;

	struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;

	bool stuck;
@@ -72,7 +73,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine) 
	stuck &= instdone_unchanged(instdone.slice_common,

				    &accu_instdone->slice_common);



	for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {

		stuck &= instdone_unchanged(instdone.sampler[slice][subslice],

					    &accu_instdone->sampler[slice][subslice]);

		stuck &= instdone_unchanged(instdone.row[slice][subslice],

drivers/gpu/drm/i915/gt/intel_sseu.c

+46 −1
Original line number Diff line number Diff line
@@ -8,6 +8,17 @@ 
#include "intel_lrc_reg.h"

#include "intel_sseu.h"



void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

			 u8 max_subslices, u8 max_eus_per_subslice)

{

	sseu->max_slices = max_slices;

	sseu->max_subslices = max_subslices;

	sseu->max_eus_per_subslice = max_eus_per_subslice;



	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);

	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);

}



unsigned int

intel_sseu_subslice_total(const struct sseu_dev_info *sseu)

{
@@ -19,10 +30,44 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) 
	return total;

}



void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,

			       u8 *to_mask)

{

	int offset = slice * sseu->ss_stride;



	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);

}



u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)

{

	int i, offset = slice * sseu->ss_stride;

	u32 mask;



	GEM_BUG_ON(slice >= sseu->max_slices);



	GEM_BUG_ON(sseu->ss_stride > sizeof(mask));



	for (i = 0; i < sseu->ss_stride; i++)

		mask |= (u32)sseu->subslice_mask[offset + i] <<

			i * BITS_PER_BYTE;



	return mask;

}



void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,

			      u32 ss_mask)

{

	int i, offset = slice * sseu->ss_stride;



	for (i = 0; i < sseu->ss_stride; i++)

		sseu->subslice_mask[offset + i] =

			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;

}



unsigned int

intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)

{

	return hweight8(sseu->subslice_mask[slice]);

	return hweight32(intel_sseu_get_subslices(sseu, slice));

}



u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,

drivers/gpu/drm/i915/gt/intel_sseu.h

+26 −1
Original line number Diff line number Diff line
@@ -15,10 +15,11 @@ struct drm_i915_private; 
#define GEN_MAX_SLICES		(6) /* CNL upper bound */

#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */

#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)

#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)



struct sseu_dev_info {

	u8 slice_mask;

	u8 subslice_mask[GEN_MAX_SLICES];

	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];

	u16 eu_total;

	u8 eu_per_subslice;

	u8 min_eu_in_pool;
@@ -33,6 +34,9 @@ struct sseu_dev_info { 
	u8 max_subslices;

	u8 max_eus_per_subslice;



	u8 ss_stride;

	u8 eu_stride;



	/* We don't have more than 8 eus per subslice at the moment and as we

	 * store eus enabled using bits, no need to multiply by eus per

	 * subslice.
@@ -63,12 +67,33 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 
	return value;

}



static inline bool

intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,

			int subslice)

{

	u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +

				      subslice / BITS_PER_BYTE];



	return mask & BIT(subslice % BITS_PER_BYTE);

}



void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

			 u8 max_subslices, u8 max_eus_per_subslice);



unsigned int

intel_sseu_subslice_total(const struct sseu_dev_info *sseu);



unsigned int

intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);



void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,

			       u8 *to_mask);



u32  intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);



void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,

			      u32 ss_mask);



u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,

			 const struct intel_sseu *req_sseu);

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