MIPS: R2: Fix problem with code that incorrectly modifies ebase. (9fb4c2b9) · Commits · 戴 / test

Commit had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by:

David VomLehn <dvomlehn@cisco.com> Signed-off-by:

Chris Dearman <chris@mips.com> Signed-off-by:

Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/traps.c

+7 −5

Original line number	Diff line number	Diff line
		@@ -1520,7 +1520,9 @@ void __cpuinit per_cpu_trap_init(void)
		#endif /* CONFIG_MIPS_MT_SMTC */

		if (cpu_has_veic \|\| cpu_has_vint) {
		unsigned long sr = set_c0_status(ST0_BEV);
		write_c0_ebase(ebase);
		write_c0_status(sr);
		/* Setting vector spacing enables EI/VI mode */
		change_c0_intctl(0x3e0, VECTORSPACING);
		}
		@@ -1602,8 +1604,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
		#ifdef CONFIG_64BIT
		unsigned long uncached_ebase = TO_UNCAC(ebase);
		#endif
		if (cpu_has_mips_r2)
		uncached_ebase += (read_c0_ebase() & 0x3ffff000);

		if (!addr)
		panic(panic_null_cerr);
		@@ -1635,9 +1635,11 @@ void __init trap_init(void)
		return; /* Already done */
		#endif

		if (cpu_has_veic \|\| cpu_has_vint)
		ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
		else {
		if (cpu_has_veic \|\| cpu_has_vint) {
		unsigned long size = 0x200 + VECTORSPACING*64;
		ebase = (unsigned long)
		__alloc_bootmem(size, 1 << fls(size), 0);
		} else {
		ebase = CAC_BASE;
		if (cpu_has_mips_r2)
		ebase += (read_c0_ebase() & 0x3ffff000);

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