MIPS: Consider value of c0_ebase when computing value of exception base. (566f74f6) · Commits · 戴 / test

arch/mips/kernel/traps.c

+9 −4

Original line number	Original line	Diff line number	Diff line
	@@ -1555,6 +1555,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
	#ifdef CONFIG_64BIT		#ifdef CONFIG_64BIT
	unsigned long uncached_ebase = TO_UNCAC(ebase);		unsigned long uncached_ebase = TO_UNCAC(ebase);
	#endif		#endif
			if (cpu_has_mips_r2)
			ebase += (read_c0_ebase() & 0x3ffff000);

	if (!addr)		if (!addr)
	panic(panic_null_cerr);		panic(panic_null_cerr);
	@@ -1588,8 +1590,11 @@ void __init trap_init(void)

	if (cpu_has_veic \|\| cpu_has_vint)		if (cpu_has_veic \|\| cpu_has_vint)
	ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);		ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
	else		else {
	ebase = CAC_BASE;		ebase = CAC_BASE;
			if (cpu_has_mips_r2)
			ebase += (read_c0_ebase() & 0x3ffff000);
			}

	per_cpu_trap_init();		per_cpu_trap_init();

	@@ -1697,11 +1702,11 @@ void __init trap_init(void)

	if (cpu_has_vce)		if (cpu_has_vce)
	/* Special exception: R4[04]00 uses also the divec space. */		/* Special exception: R4[04]00 uses also the divec space. */
	memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);		memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
	else if (cpu_has_4kex)		else if (cpu_has_4kex)
	memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);		memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
	else		else
	memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);		memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);

	signal_init();		signal_init();
	#ifdef CONFIG_MIPS32_COMPAT		#ifdef CONFIG_MIPS32_COMPAT

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